RENESAS CS80C8896S2490

The Intersil 80C88 high performance 8-/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Full TTL compatibility (with the exception of CLOCK) and industry-standard operation allow use of existing NMOS 8088 hardware and Intersil CMOS peripherals. Complete software compatibility with the 80C86, 8086, and 8088 microprocessors allows use of existing software in new designs. All 80C88 circuitry is static in design. Internal registers, counters and latches are static and require not refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS 80C88 can operate from DC to the specified upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The 80C88 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for start-up. Static design also allows very low frequency operation (as low as DC). In a power critical situation, this can provide extremely low power operation since 80C88 power dissipation is directly related to operation frequency. As the system frequency is reduced, so is the operating power until, at a DC input frequency, the power requirement is the 80C88 standby current. The internal functions of the 80C88 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the CPU block diagram. These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 4-bytes of the instruction stream can be queued while waiting for decoding and execution. The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 1-byte in the queue, the BIU will attempt a byte fetch memory cycle. This greatly reduces “dead time” on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU. The execution unit receives pre-fetched instructions from the BIU queue and provides unrelocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage. The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 milli

• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086, 8088
• 8-Bit Data Bus Interface; 16-Bit Internal Architecture
• Completely Static CMOS Design - DC ...... 5MHz (80C88) - DC ...8MHz (80C88-2)
• Low Power Operation - ICCSB...... 500μA Maximum - ICCOP ...10mA/MHz Maximum
• 1 Megabyte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Ranges - C80C88 ...... 0°C to +70°C - I80C88 ...... -40°C to +85°C - M80C88 ...... -55°C to +125°C
• Pb-Free Available (RoHS Compliant)

• Small systems
• Large applications (e.g., multiprocessing)
• Compatible with existing NMOS 8088 hardware and Intersil CMOS peripheral designs
• System debugging or power-critical applications
• Efficient memory bus utilization
• Multiplexed or non-multiplexed bus support
• For use with 82C86 or 82C87 transceivers
• For use with 82C88 bus controller
• Hardware lock, queue status, and two request/grant interfaces
• Coprocessor support in local and remote bus configurations
• Compatible with 8085 design upgrades
• Initialization and startup operations
• Interrupt operations