TI SN74HCS74PWR

This device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt-trigger action to accommodate slow or noisy input signals. Setting the preset (PRE) input low drives the output high. Setting the clear (CLR) input low resets the output low. The preset and clear functions are asynchronous and independent of all other input levels. When PRE and CLR are inactive (high), data meeting the setup time requirements at the data (D) input is transferred to the outputs (Q, Q̄) on the positive edge of the clock (CLK) pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the CLK input signal. After the hold time interval has elapsed, data at the data (D) input may be changed without affecting the levels at the outputs (Q, Q̄).

• Wide supply voltage range: 2V to 6V
• Schmitt-trigger inputs for slow or noisy input signals
• Low power consumption
• ICC typical: 100nA
• Input leakage current typical: ±100nA
• Output drive: ±7.8mA at 6V
• Operating ambient temperature range: -40℃ to +125℃, TA

• Convert momentary switch to toggle switch
• Maintain signal input during controller reset
• Slow edge rate signals for operation in high-noise environments
• Divide clock signal by two