TI TMS320C6211BZFN150

The TMS320C62xTM DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000TM DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTITm very-long-instruction-word (VLiW) architecture, making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1 D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPl), and a glueless external memory interface.

• Eight 32-Bit Instructions/Cycle
• C6211, C6211B, C6711, and C6711B are Pin-Compatible
• 150-, 167-MHz Clock Rates
• 6.7-, 6-ns Instruction Cycle Time
• 1200, 1333 MIPS
• Extended Temperature Device (C6211B)
• Eight Highly Independent Functional Units: Six ALUs (32-/40-Bit), Two 16-Bit Multipliers (32-Bit Results)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Byte-Addressable (8-, 16-, 32-Bit Data)
• 8-Bit Overflow Protection
• Saturation
• Bit-Field Extract, Set, Clear
• Bit-Counting
• Normalization
• 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
• 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
• 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
• Boot Mode: HPl, 8-, 16-, and 32-Bit ROM Boot
• Endianness: Little Endian, Big Endian
• 32-Bit External Memory Interface (EMIF)
• Glueless Interface to Asynchronous Memories: SRAM and EPROM
• Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
• 512M-Byte Total Addressable External Memory Space
• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• 16-Bit Host-Port Interface (HPI)
• Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports (McBSPs)
• Direct Interface to T1/E1, MVIP, SCSA Framers
• ST-Bus-Switching Compatible
• Up to 256 Channels Each
• AC97-Compatible
• Serial-Peripheral-Interface (SPI) Compatible (Motorola)
• Two 32-Bit General-Purpose Timers
• Flexible Phase-Locked-Loop (PLL) Clock Generator
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
• 0.18-μm/5-Level Metal Process
• CMos Technology
• 3.3-V I/Os, 1.8-V Internal

• Multi-channel and multi-function applications
• Direct interface with T1/E1, MVIP, SCSA framers
• ST-Bus-Switching compatible
• AC97 compatible
• SPI compatible (Motorola™)