NXP DSP56854FGE

This device is a member of the 56800E core-based controller family, integrating DSP processing capability with microcontroller functionality on a single chip, along with a flexible set of peripherals to form a highly cost-effective solution. Its low cost, configuration flexibility, and compact program code make it suitable for a wide range of applications. The device includes numerous peripherals particularly useful for low-end Internet appliance applications and low-end client applications such as telephones, portable devices, Internet audio, point-of-sale systems, noise suppression, ID tag readers, sonic/subsonic detectors, secure access devices, remote metering, sonic alarms, and more. The 56800E core employs a Harvard architecture consisting of three processing units operating in parallel, allowing up to six operations per instruction cycle. Its microprocessor-style programming model and optimized instruction set facilitate the generation of efficient, compact DSP and control code. The instruction set is also highly effective for C compilers, accelerating the development of optimized control applications. The device supports program execution from either internal or external memory. Two data operands can be accessed from on-chip data RAM per instruction cycle. It also provides two dedicated external interrupt lines and up to 41 general-purpose I/O lines, depending on peripheral configuration. The controller contains 16K words of program RAM, 16K words of data RAM, and 1K word of boot ROM, and also supports program execution from external memory. In addition, it provides a complete set of standard programmable peripherals, including an 8-bit parallel host interface, an enhanced synchronous serial interface, a serial peripheral interface, two serial communication interfaces, and a quad timer. If their primary functions are not required, the host interface, enhanced synchronous serial interface, serial peripheral interface, serial communication interfaces, four chip selects, and quad timer can be used as general-purpose I/O.

• Digital Signal Processing Core: Efficient 16-bit engine with dual Harvard architecture; 120 MIPS at 120MHz core frequency; single-cycle 16×16-bit parallel multiply-accumulate; four 36-bit accumulators (with guard bits); 16-bit bidirectional barrel shifter; parallel instruction set with dedicated DSP addressing modes; hardware DO and REP loops; three internal address buses and one external address bus; four internal data buses and one external data bus; instruction set supporting both DSP and controller functions; four hardware interrupt levels; five software interrupt levels; controller-style addressing modes and instructions for compact code; efficient C compiler with local variable support; software subroutine and interrupt stack depth limited only by memory; JTAG/enhanced on-chip emulation debug and programming interface.
• Memory: Harvard architecture allows up to three simultaneous accesses to program and data memory; on-chip memory: 16K×16-bit program SRAM, 16K×16-bit data SRAM, 1K×16-bit boot ROM; external memory expansion: up to 2M words of program memory or up to 8M words of data memory; chip select logic for glueless interface with ROM and SRAM.
• Peripheral Circuits: General-purpose 16-bit quad timer; two serial communication interfaces; serial peripheral interface; enhanced synchronous serial interface module; computer operating properly/watchdog timer; JTAG/enhanced on-chip emulation for non-intrusive real-time debugging; six-channel independent DMA; 8-bit parallel master port; real-time clock; up to 41 general-purpose I/Os (each peripheral I/O pin can alternatively function as general-purpose I/O when its primary function is not required).
• Power Consumption: Fabricated in high-density CMOS process with 3.3V TTL-compatible digital inputs; wait and stop modes available.