ADI ADSP-2189NKSTZ-320

The ADSP-218xN series consists of six single chip microcomputers optimized for digital signal processing applications. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision. ADSP-218xN series members combine the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. ADSP-218xN series members integrate up to 256K bytes of onchip memory configured as up to 48K words (24-bit) of program RAM, and up to 56K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xN is available in a 100-lead LQFP package and 144-ball BGA. Fabricated in a high-speed, low-power, 0.18 µm CMOS process, ADSP-218xN series members operate with a 12.5 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-218xN’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xN series members can:

• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer

• 12.5 ns Instruction cycle time @ 1.8 V (internal), 80 MIPS sustained performance
• Single-cycle instruction execution
• Single-cycle context switch
• 3-bus architecture allows dual operand fetches in every instruction cycle
• Multifunction instructions
• Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down condition
• Low power dissipation in idle mode
• ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions
• Up to 256K byte of on-chip RAM, configured Up to 48K words program memory RAM Up to 56K words data memory RAM
• Dual-purpose program memory for both instruction and data storage
• Independent ALU, multiplier/accumulator, and barrel shifter computational units
• Two independent data address generators
• Powerful program sequencer provides zero overhead looping conditional instruction execution
• Programmable 16-bit interval timer with prescaler
• 100-lead LQFP and 144-ball BGA
• Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation All inputs tolerate up to 3.6 V regardless of mode
• 16-bit internal DMA port for high-speed access to on-chip memory (mode selectable)
• 4M-byte memory interface for storage of data tables and program overlays (mode selectable)
• 8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable)
• Programmable memory strobe and separate I/O memory space permits “glueless” system design
• Programmable wait state generation
• Two double-buffered serial ports with companding hardware and automatic data buffering
• Automatic booting of on-chip program memory from bytewide external memory, for example, EPROM, or through internal DMA Port
• Six external interrupts
• 13 programmable flag pins provide flexible system signaling
• UART emulation through software SPORT reconfiguration
• ICE-Port emulator interface supports debugging in final systems