MICROCHIP LAN91C93I-MU
| Hersteller | |
| Herst.-Teilenr. | LAN91C93I-MU |
| LCSC-Nr. | C638307 |
| Verp. | - |
| Kundennummer | |
| Hauptmerkm. | Power Over Ethernet (PoE) Controllers RoHS |
| Datenblatt | MICROCHIP LAN91C93I-MU |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Power Management (PMIC)/Power Over Ethernet (PoE) Controllers | |
| Hersteller | MICROCHIP | |
| Verp. | - | |
| Features | Low-power mode;Programmable LED indication;Power-on reset |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Power Management (PMIC)/Power Over Ethernet (PoE) Controllers | |
| Hersteller | MICROCHIP |
| Typ | Beschreibung | |
|---|---|---|
| Verp. | - | |
| Features | Low-power mode;Programmable LED indication;Power-on reset |
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Merkmale
KI-Übersetzung
- Non-PCI Single-Chip Ethernet Controller
- Fully Supports Full Duplex Switched Ethernet
- Supports Enhanced Transmit Queue Management
- 6K Bytes of On-Chip RAM Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards
- Automatic Detection of TX/RX Polarity Reversal
- Simultasking Early Transmit and Early Receive Functions
- Enhanced Early Transmit Function
- Receive Counter for Enhanced Early Receive
- Hardware Memory Management Unit
- Optional Configuration via Serial EEPROM Interface (Jumperless)
- Supports single 5V or 3.3V VCC Design
- Supports Mixed Voltage External PHY Designs
- Supports Industrial Temp -40℃ to 85℃
- Low Power CMOS Design
- 100 Pin QFP and TQFP (1.0mm body Thickness) packages; green, lead-free packages also available
- Direct Interface to local bus, with No Wait States
- 16 Bit Data and Control Paths
- Fast Access Time
- Pipelined Data Path
- Handles Block Word Transfers for any Alignment High Performance Chained ("Back-to-Back") Transmit and Receive
- Dynamic Memory Allocation Between Transmit and Receive
- Flat Memory Structure for Low CPU Overhead
- Buffered Architecture, Insensitive to Bus Latencies (No Overruns/Underruns)
- Supports Boot PROM for Diskless local bus Applications
Garantie auf jede Bestellung
100% Authentisch · 30-Tage-Rückgabe oder -Umtausch
Nicht vorrätig
Benachrichtigen
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
| Stk. | E-Preis(Nur als Referenz) | Gesamtbetrag |
|---|---|---|
| 1+ | $ 21.6935 | $ 21.69 |
| 200+ | $ 8.395 | $ 1679.00 |
| 500+ | $ 8.1002 | $ 4050.10 |
| 1,000+ | $ 7.9551 | $ 7955.10 |
Standardgehäuse90/Full Tray | ||
Besserer Preis bei größerer Menge?
$
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Power Management (PMIC)/Power Over Ethernet (PoE) Controllers | |
| Hersteller | MICROCHIP | |
| Verp. | - | |
| Features | Low-power mode;Programmable LED indication;Power-on reset |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Power Management (PMIC)/Power Over Ethernet (PoE) Controllers | |
| Hersteller | MICROCHIP |
| Typ | Beschreibung | |
|---|---|---|
| Verp. | - | |
| Features | Low-power mode;Programmable LED indication;Power-on reset |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- Non-PCI Single-Chip Ethernet Controller
- Fully Supports Full Duplex Switched Ethernet
- Supports Enhanced Transmit Queue Management
- 6K Bytes of On-Chip RAM Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards
- Automatic Detection of TX/RX Polarity Reversal
- Simultasking Early Transmit and Early Receive Functions
- Enhanced Early Transmit Function
- Receive Counter for Enhanced Early Receive
- Hardware Memory Management Unit
- Optional Configuration via Serial EEPROM Interface (Jumperless)
- Supports single 5V or 3.3V VCC Design
- Supports Mixed Voltage External PHY Designs
- Supports Industrial Temp -40℃ to 85℃
- Low Power CMOS Design
- 100 Pin QFP and TQFP (1.0mm body Thickness) packages; green, lead-free packages also available
- Direct Interface to local bus, with No Wait States
- 16 Bit Data and Control Paths
- Fast Access Time
- Pipelined Data Path
- Handles Block Word Transfers for any Alignment High Performance Chained ("Back-to-Back") Transmit and Receive
- Dynamic Memory Allocation Between Transmit and Receive
- Flat Memory Structure for Low CPU Overhead
- Buffered Architecture, Insensitive to Bus Latencies (No Overruns/Underruns)
- Supports Boot PROM for Diskless local bus Applications
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Typ | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Typ | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

