GSI Technology GS8662QT37BGD-333I

GS8662QT07/10/19/37BD complies with the SigmaQuad-II+ SRAM pin standard for independent I/O synchronous SRAM. They are 75,497,472-bit (72Mb) SRAMs, part of a low-power, low-voltage HSTL I/O SRAM family designed to operate at the speeds required for cost-effective, high-performance networking systems.

• 2.0 clock latency
• SigmaQuad interface with simultaneous read and write
• JEDEC standard pinout and package
• Double data rate interface
• Byte write control sampled at data input
• Dual-range on-die termination (ODT) on data (D), byte write (BW), and clock (K, K) inputs
• Burst length of 2 read and write
• 1.8 V ±100 mV core supply voltage
• 1.5 V or 1.8 V HSTL interface
• Pipelined read operation
• Fully consistent read/write pipeline
• ZQ pin for programmable output drive strength
• Data valid pin (QVLD) support
• IEEE 1149.1 JTAG-compatible boundary scan
• 165-ball, 13 mm × 15 mm, 1 mm ball pitch BGA package
• RoHS-compliant 165-ball BGA package available

• High-performance network systems