TI SNJ54LS390J
| Hersteller | |
| Herst.-Teilenr. | SNJ54LS390J |
| LCSC-Nr. | C5217982 |
| Verp. | CDIP-16 |
| Kundennummer | |
| Hauptmerkm. | 2 35MHz CDIP-16 Counters, Dividers |
| Datenblatt | TI SNJ54LS390J |
Produktspezifikationen
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Hersteller | TI | |
| Verp. | CDIP-16 | |
| Logic Family | 54LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | Up Counter | |
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 2 | |
| Count Rate | 35MHz | |
| Features | Programmable divide ratio;Reset function |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Hersteller | TI | |
| Verp. | CDIP-16 | |
| Logic Family | 54LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | Up Counter |
| Typ | Beschreibung | |
|---|---|---|
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 2 | |
| Count Rate | 35MHz | |
| Features | Programmable divide ratio;Reset function |
Beschreibung
Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to implement. two individual four-bit counters in a single package. The '390 and 'LS390 incorporate dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to divide-by-100. When connected as a bi-quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The '393 and 'LS393 each comprise two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256.The'390,'LS390,'393, and 'LS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals.
Merkmale
- Dual Versions of the Popular '90A, 'LS90 and '93A, 'LS93
- '390, 'LS390 ... lndividual Clocks for A and B Flip-Flops Provide Dual ÷2 and ÷5 Counters
- '393, 'LS393 ... Dual 4-Bit Binary Counter with Individual Clocks
- All Have Direct Clear for Each 4-Bit Counter
- Dual 4-Bit Versions Can Significantly Improve System Densities by Reducing Counter Package Count by 50%
- Typical Maximum Count Frequency ... 35 MHz
- Buffered Outputs Reduce Possibility of Collector Commutation
Anwendungen
- Counter function for different division ratios
- Timing signal generation for digital systems
| Stk. | E-Preis | Gesamtbetrag |
|---|---|---|
| 1+ | $ 34.1756 | $ 34.18 |
| 25+ | $ 32.4958 | $ 812.40 |
Standardgehäuse25/Full Tube | ||
Produktspezifikationen
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Hersteller | TI | |
| Verp. | CDIP-16 | |
| Logic Family | 54LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | Up Counter | |
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 2 | |
| Count Rate | 35MHz | |
| Features | Programmable divide ratio;Reset function |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Hersteller | TI | |
| Verp. | CDIP-16 | |
| Logic Family | 54LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | Up Counter |
| Typ | Beschreibung | |
|---|---|---|
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 2 | |
| Count Rate | 35MHz | |
| Features | Programmable divide ratio;Reset function |
Beschreibung
Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to implement. two individual four-bit counters in a single package. The '390 and 'LS390 incorporate dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to divide-by-100. When connected as a bi-quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The '393 and 'LS393 each comprise two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256.The'390,'LS390,'393, and 'LS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals.
Merkmale
- Dual Versions of the Popular '90A, 'LS90 and '93A, 'LS93
- '390, 'LS390 ... lndividual Clocks for A and B Flip-Flops Provide Dual ÷2 and ÷5 Counters
- '393, 'LS393 ... Dual 4-Bit Binary Counter with Individual Clocks
- All Have Direct Clear for Each 4-Bit Counter
- Dual 4-Bit Versions Can Significantly Improve System Densities by Reducing Counter Package Count by 50%
- Typical Maximum Count Frequency ... 35 MHz
- Buffered Outputs Reduce Possibility of Collector Commutation
Anwendungen
- Counter function for different division ratios
- Timing signal generation for digital systems
C5217982 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Typ | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Typ | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



