Infineon/CYPRESS CY7C1354A-166AI

The CY7C1354A and CY7C1356A SRAMs are designed to eliminate dead cycles during transitions from read to write operations or vice versa. These SRAMs are optimized for 100% bus utilization, achieving Zero Bus Latency (ZBL™)/No Bus Latency (NoBL™). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, along with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operations. These SRAMs employ a high-speed, low-power CMOS design using advanced triple-layer polysilicon, dual-layer metal technology. Each memory cell consists of four transistors and two high-value resistors. All synchronous inputs are gated by registers controlled by a positive edge-triggered clock input (CLK). Synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (CE, CE₂, and CE₃), the burst initiation input (ADV/LD), clock enable (CEN), byte write enables (BWa, BWb, BWc, and BWd), and read/write control (WEN). BWc and BWd apply to the CY7C1354A only. Address and control signals are applied to the SRAM in one clock cycle, and the associated data (read or write) appears two cycles later. The clock enable (CEN) pin allows the operation of the CY7C1354A/CY7C1356A to be suspended when necessary. When CEN is HIGH, all synchronous inputs are ignored and the internal device registers retain their previous values. Three chip enable pins (CE̅, CE₂, CE̅₃) allow the user to deselect the device when needed. If any of these three pins is deasserted while ADV/LD is LOW, no new memory operation can be initiated, and any ongoing burst cycle will halt. However, any pending data transfer (read or write) will complete. The data bus will be placed in a high-impedance state two cycles after the chip is deselected or a write cycle is initiated. The CY7C1354A and CY7C1356A feature an on-chip 2-bit burst counter. In burst mode, the CY7C1354A and CY7C1356A provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin, which selects between linear and interleaved burst sequences. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or to increment the internal burst counter (ADV/LD = HIGH). Output enable (OE), sleep enable (ZZ), and burst sequence select (MODE) are asynchronous signals. OE can be used to disable the outputs at any given time. If ZZ is not used, it can be tied to ground. Four pins are dedicated to JTAG test functionality. The JTAG circuit is used to serially shift data between devices. JTAG inputs use LVTTL/LVCMOS levels to shift data in this test operation mode.

• Zero Bus Latency (ZBL™), no dead cycles between read and write
• Fast clock speeds: 200, 166, 133, 100 MHz
• Fast access times: 3.2, 3.6, 4.2, 5.0 ns
• Internal synchronous registered outputs, no OE control required
• Single 3.3V ±5% VCC supply
• Independent VCCQ for 3.3V or 2.5V I/O
• Single WEN (read/write) control pin
• Positive clock edge triggered; address, data, and control signal registers for fully pipelined operation
• Interleaved or linear quad-word burst capability
• Individual byte write (BWa–BWd) control (can be tied to GND)
• CEN pin for clock enable and suspend operation
• Three chip enables for simple depth expansion
• Automatic power-down via ZZ mode or CE deselect
• JTAG boundary scan
• Low-profile 119-bump, 14mm × 22mm BGA and 100-pin TQFP packages