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RENESAS 8T49N283C-999NLGI8

Hersteller
Herst.-Teilenr.
8T49N283C-999NLGI8
LCSC-Nr.
C2665636
Verp.
VFQFPN-56(8x8)
Kundennummer
Hauptmerkm.
1GHz 2.375V~3.465V I2C 8 VFQFPN-56(8x8) Clock Generators, PLLs, Frequency Synthesizers RoHS
DatenblattRENESAS 8T49N283C-999NLGI8
Alternativteile8
Garantie auf jede Bestellung
100% Authentisch · 30-Tage-Rückgabe oder -Umtausch
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Benachrichtigen
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 27.8522$ 27.85
200+$ 10.7793$ 2155.86
500+$ 10.3997$ 5199.85
1,000+$ 10.213$ 10213.00
Standardgehäuse3000/Full Reel
Besserer Preis bei größerer Menge?
$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers
HerstellerRENESAS
Verp.VFQFPN-56(8x8)
Operating Temperature-40℃~+85℃
Clock/OscillatorExternal
Output Frequency(Max)1GHz
Voltage - Supply2.375V~3.465V
Period Jitter, Peak-to-Peak-;-
Phase OffsetSupport
InterfaceI2C
Features-
InputLVCMOS;LVDS;LVPECL
Output LevelLVPECL;LVDS;LVCMOS
Phase Jitter-
Number of Outputs8

Merkmale

KI-Übersetzung
  • Two independent fractional feedback PLLs, usable as jitter attenuators and frequency translators
  • Six integer and two fractional output dividers, generating up to 8 different output frequencies ranging from 8kHz to 1GHz
  • Four of these frequencies are fully independent of each other and of the input; the remaining four are related frequencies
  • All eight outputs selectable among LVPECL, LVDS, or LVCMOS output levels
  • Accepts up to two differential or single-ended input clocks and one crystal input
  • Each internal PLL can lock to a different input clock, which may be at independent frequencies
  • Each PLL can use the other input as a redundant backup for the primary clock, though in this case the two input clock frequencies must be related
  • Hitless reference switching between input clocks
  • Loss-of-signal (LOS) monitoring on all input clocks, with alarm generation upon detection of input clock failure
  • Automatic and manual hitless reference switching options
  • LOS behavior configurable to support gapped or non-gapped clocks
  • Holdover mode support per PLL
  • Holdover mode initiated from the point where loss of all applicable input references is detected, with initial accuracy of ±50ppb
  • Maintains a historical average operating point for each PLL, which can be returned to at a limited phase slope during holdover mode
  • No restrictions on input-to-output frequency translation; supports all FEC rates including the new version of ITU-T Recommendation G.709 (2009), with most translation errors at 0ppm
  • Per-PLL register-selectable loop bandwidth ranging from 0.5Hz to 512Hz
  • Individual phase delay settings per output to enable output-to-output alignment
  • Output enable input and lock, holdover, and LOS status outputs
  • Programmable via I²C interface
  • I²C master capability for reading register configurations from an external EEPROM

Anwendungen

KI-Übersetzung
  • OTN or SONET/SDH equipment line cards (up to OC-192 with FEC rate support)
  • OTN demapping (gapped clock and DCO modes)
  • Gigabit and Terabit IP switches/routers, including Synchronous Ethernet support
  • Wireless base station baseband
  • Data communications
  • SDH/SONET and Synchronous Ethernet clock support, including all FEC rate conversions

Alternativteile

MPNHerstellerVerpackungVerfügbarkeitStückpreis
8T49N283C-998NLGI8RENESASVFQFPN-56(8x8)0$ 27.8522
8T49N285A-999NLGIRENESASVFQFPN-56(8x8)0$ 23.3587
8T49N285A-998NLGIRENESASVFQFPN-56(8x8)0$ 6.641
8T49N285-998NLGIRENESASVFQFPN-56(8x8)0$ 19.1587
8T49N285A-999NLGI8RENESASVFQFPN-56(8x8)0$ 12.2144
8T49N283C-998NLGI#RENESASVFQFPN-56(8x8)0$ 28.4308
8T49N287A-999NLGI#RENESASVFQFPN-56(8x8)0$ 25.3892
8T49N285A-998NLGI8RENESASVFQFPN-56(8x8)0$ 12.2144