micron MT41K1G8TRF-125 IT:E TR

8Gb (TwinDie™) DDR3L SDRAM (1.35V) utilizes Micron's 4Gb DDR3L SDRAM die (essentially two 4Gb DDR3L SDRAM die sets). For specifications not included in this document, refer to the Micron 4Gb DDR3 SDRAM data sheet. The specifications for base part number MT41K1G4 correspond to TwinDie fabricated part number MT41K2G4; the specifications for base part number MT41K512M8 correspond to TwinDie fabricated part number MT41K1G8. The TwinDie DDR3L SDRAM is a high-speed CMOS dynamic random access memory device internally configured as two 8-bank DDR3L SDRAM devices. Although each die within the dual-die package is tested individually, some TwinDie test results may differ from those of the same die in a monolithic package. DDR3L SDRAM uses a double data rate architecture for high-speed operation. The double data rate architecture is an 8n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. Read and write accesses to the DDR3L SDRAM are burst-oriented. An access begins at a selected location and continues for a programmed number of locations in a programmed sequence. Access begins with the registration of an ACTIVATE command, followed by a READ or WRITE command. Address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. Address bits registered coincident with the READ or WRITE command — including CSn#, BAn, and An — are used to select the chip set, bank, and starting column location for the burst access. This data sheet provides a general description, package dimensions, and package notes. For complete information on individual die initialization, register definitions, command descriptions, and die operations, refer to the Micron monolithic DDR3L data sheet.

• Uses 4Gb Micron die
• Two component stacks (including dual CS#, ODT, CKE, and ZQ pins)
• Eight internal banks per component stack for concurrent operation
• VDD = VDDQ = 1.35V (1.283 - 1.45V); backward compatible with VDD = VDDO = 1.5V ± 0.075V
• 1.35V center-tapped push-pull I/O
• JEDEC standard pin layout
• Thin package
• TC: 0°C to 95°C
• 0°C to 85°C: 8192 refresh cycles in 64ms
• 85°C to 95°C: 8192 refresh cycles in 32ms
• Available in industrial temperature (IT) version (version E)
• Timing - Cycle time: 1.071ns @ CL = 13 (DDR3L-1866) - 107; 1.25ns @ CL = 11 (DDR3L-1600) - 125; 1.5ns @ CL = 9 (DDR3L-1333) - 15E; 1.87ns @ CL = 7 (DDR3L-1066) - 187E
• Self-refresh
• Standard: None
• Operating temperature: Commercial grade (0°C ≤ TC ≤ 95°C) None; Industrial grade (-40°C ≤ TC ≤ 95°C) Version E IT