Insignis Technology Corporation NLQ83PFS-8NAT TR

LPDDR4 SDRAM can be organized as 1 or 2 channels per device, with each channel having 8 banks and 16 bits. The product uses a double data rate architecture for high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture, with an interface designed to transfer two data words per clock cycle on the I/O pins. The product provides fully synchronous operation, referenced to both rising and falling edges of the clock. The data path is internally pipelined, prefetching 16n bits to achieve very high bandwidth. This LPDDR4 device uses a 2 or 4 clock architecture on the command/address (CA) bus to reduce the number of input pins in the system. The 6-bit CA bus carries command, address, and bank information. Each command uses 1, 2, or 4 clock cycles, during which command information is transferred on the positive edge of the clock.

• JEDEC compliant
• AEC-Q100 compliant
• Fast clock rates: 1200/1600MHz
• Low-voltage core and I/O supply:
  • VDD1 = 1.8V (1.7V ~ 1.95V)
  • VDD2 = 1.1V (1.06V ~ 1.17V)
  • VDDQ = 1.1V (1.06V ~ 1.17V)
• Operating temperature range:
  • Extended Test (ET): TC = 0 ~ 85°C
  • Industrial (IT): TC = -40 ~ 85°C
  • Automotive (AT): TC = -40 ~ 105°C
• JEDEC clock jitter specification support
• On-die ECC:
  • Single-bit error correction (per 64 bits) for maximum reliability
  • Per-channel optional ERR output signal indicating ECC events
  • ECC registers for ECC function control
• Configurations:
  • 2 channels per device at x32
  • 1 channel per device at x16
• 8 internal banks per channel
• 16n-bit prefetch architecture
• Single data rate (multi-cycle) CMD/ADR bus
• Differential bidirectional data strobe per data byte
  • DQS and DQS#
• DMI pin supporting write data masking and DBI function
• Programmable read and write latency
• Programmable and dynamically adjustable burst length
• Non-target DRAM ODT control support
• Per-bank targeted refresh for concurrent bank operation and simplified command scheduling
• Selectable output drive strength (DS)
• Dynamic ODT:
  • DQ ODT: VSSQ termination
  • CA ODT: VSS termination
• On-die temperature sensor for self-refresh rate control
• On-die temperature sensor with status readable from MR4
• Interface: LVSTL
• Internal VREF and VREF training
• ZQ calibration
• RoHS compliant
• Package: lead-free and halogen-free
  • 2Gb/4Gb: 200-ball 10×14.5×0.8mm FBGA
  • 8Gb (dual-die): 200-ball 10×14.5×1.1mm FBGA