ISSI IS43LD32320D-18BLI-TR

IS43/46LD16640D/32320D is a 1Gbit CMOS LPDDR2 DRAM. The device is organized as 8 banks, each containing 8M x 16-bit words or 4M x 32-bit words. This product employs a double data rate architecture for high-speed operation. The double data rate architecture is fundamentally a 4N prefetch architecture, with an interface designed to transfer two data words per clock cycle on the I/O pins. The product provides fully synchronous operation, referenced to both the rising and falling edges of the clock. The data path is internally pipelined with a 4n-bit prefetch to achieve very high bandwidth.

LPDDR2-S4 is a high-speed SDRAM device internally configured as an 8-bank memory. The device contains 1,073,741 bits (1Gbit). All LPDDR2 devices employ a double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus carries command, address, and bank/row buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edges of the clock.

This LPDDR2-S4 device also employs a double data rate architecture on the DQ pins for high-speed operation. The double data rate architecture is fundamentally a 4n prefetch architecture, with an interface designed to transfer two data bits per DQ per clock cycle on the I/O pins. A single read or write access to the memory device consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core, and four corresponding n-bit wide, half clock cycle data transfers on the I/O pins.

Read and write accesses to LPDDR2 are burst-oriented; an access starts at a selected location and continues for a programmed number of locations in a programmed sequence. An access begins with the registration of an ACTIVATE command, followed by a READ or WRITE command. The address and BA bits registered concurrently with the ACTIVATE command are used to select the row and bank to be accessed. The address bits registered concurrently with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

LPDDR2 must be initialized prior to normal operation. The following sections provide detailed information on device initialization, register definitions, command descriptions, and device operation.

• Low-voltage core and I/O supplies: VDD2 = 1.14 - 1.30V, VDDCA/VDDQ = 1.14 - 1.30V, VDD1 = 1.70 - 1.95V; High Speed Unterminated Logic (HSUL_12) I/O interface
• Clock frequency range: 10MHz to 533MHz (data rate range: 20Mbps to 1066Mbps per I/O)
• 4-bit prefetch DDR architecture
• Multiplexed, double data rate, command/address inputs; eight internal banks for concurrent operation
• Bidirectional/differential data strobe per data byte (DQS/DQS#)
• Programmable read/write latency (RL/WL) and burst length (4, 8, or 16); ZQ calibration
• On-chip temperature sensor for self-refresh rate control
• Partial Array Self-Refresh (PASR)
• Deep Power Down (DPD) mode
• Operating temperature: Commercial (Tc = 0°C to 85°C); Industrial (Tc = -40°C to 85°C); Automotive A1 (Tc = -40°C to 85°C); Automotive A2 (Tc = -40°C to 105°C); Automotive A25 (Tc = -40°C to 115°C)
• Configurations: 64Mx16 (8M x 16 x 8 banks); 32Mx32 (4M x 32 x 8 banks)
• Green packages: 134-ball BGA for x16/x32; 168-ball PoP BGA for x32