Intel/Altera EPM7256AEQC208-10

MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. The MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages. MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times.

• High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture
• 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
• MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
• EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
• Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
• Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
• Enhanced ISP features
• Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
• ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
• Pull-up resistor on I/O pins during in-system programming
• Pin-compatible with the popular 5.0-V MAX 7000S devices
• High-density PLDs ranging from 600 to 10,000 usable gates
• Extended temperature range
• 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz
• MultiVolt I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
• Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGA, and plastic J-lead chip carrier (PLCC) packages
• Supports hot-socketing in MAX 7000AE devices
• Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
• PCI-compatible
• Bus-friendly architecture, including programmable slew-rate control
• Open-drain output option
• Programmable macrocell registers with individual clear, preset, clock, and clock enable controls
• Programmable power-up states for macrocell registers in MAX 7000AE devices
• Programmable power-saving mode for 50% or greater power reduction in each macrocell
• Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
• Programmable security bit for protection of proprietary designs
• 6 to 10 pin- or logic-driven output enable signals
• Two global clock signals with optional inversion
• Enhanced interconnect resources for improved routability
• Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
• Programmable output slew-rate control
• Programmable ground pins
• Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations
• Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
• Programming support with Altera’s Master Programming Unit (MPU), MasterBlaster serial/universal serial bus (USB) communications cable, ByteBlasterMV parallel port download cable, and BitBlaster serial download cable, as well as programming hardware from third-party manufacturers and any Jam STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester