MICROCHIP MCP37D21-80E/TE

The MCP37D31-80 and MCP37D21-80 are 80 Msps, 16-bit and 14-bit high-precision analog-to-digital converter, respectively, with configurable input MUX. A built-in 8-input multiplexer (MUX) is used to select the active analog input(s) depending on the user configuration. In single-channel operation, the MUX can be configured to select one of the 8-inputs. In multichannel operation, the selected inputs are sequentially sampled. The input channel selection and the channel order are configured using the user-programmable configuration register bits. The ADC core operates at up to an 80 Msps rate. In single-channel operation, the analog input is sampled at full speed. In multi-channel operation, the effective sample rate per channel is the full speed divided by the number of selected channels. For example, if all 8-input channels are used, each input channel is sampled at 10 Msps when the ADC core is running at 80 Msps. Similarly, if only 4-input channels are selected, each input channel is sampled at 20 Msps when the ADC core is running at 80 Msps. The device features harmonic distortion correction, DAC noise cancellation, power-up calibration, and always-on background calibration which enable high performance to be maintained consistently across the extended temperature range. In addition to the data conversion, the device offers exceptional user-selectable built-in digital signal postprocessing (DSPP) features that include high-order digital decimation filters, digital down-conversion (DDC), fractional delay recovery (FDR), gain and offset adjustment per channel, and continuous wave (CW) beamforming capability. The output decimation filter option improves SNR performance significantly up to 90’s dBFS with the 512x decimation setting. The built-in digital downconversion (DDC) option can offer great flexibility in advanced RF and digital communication system designs. Gain, phase and DC offset can be adjusted independently for each input channel, allowing for simplified implementation of continuous wave (CW) beamforming and ultrasound Doppler imaging applications. In dual or octal-channel mode, the Fractional Delay Recovery (FDR) feature digitally corrects the difference in sampling instance between different channels, so that all inputs appear to have been sampled at the same time. The differential full-scale analog input range is programmable up to 2.975 V P - P. The input is sampled on the rising edge of the clock. The digital output code is available after 28 clock cycles of data latency. Latency will increase if any of the digital signal post-processing (DSPP) options are enabled. The ADC output data can be coded in two's complement or offset binary representation, with or without the data randomizer option. The output data is available as full-rate CMOS or Double-Data-Rate (DDR) LVDS. Additionally, a serialized LVDS option is also available for the 16-bit octal-channel mode.

• Sample Rates:
  • 80 Msps for single-channel operation
  • 80 Msps/number of channels used
• SNR with f IN =15 MHz and -1 dBFS:
  • 73.9 dBFS (typical) at 80 Msps
• SFDR with f IN =15 MHz and -1 dBFS:
  • 93 dBc (typical) at 80 Msps
• Power Dissipation Excluding Digital I/O (80 Msps):
  • 229 mW
• Power Dissipation with CMOS Digital I/O (80 Msps):
  • MCP37D31-80: 257 mW
  • MCP37D21-80: 253 mW
• Power Dissipation with LVDS Digital I/O (80 Msps):
  • MCP37D31-80: 329 mW
  • MCP37D21-80: 320 mW
• Power-Saving Modes:
  • 79 mW during Standby
  • 22 mW during Shutdown
• Supply Voltage:
  • Digital Section: 1.2V, 1.8V
  • Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 V P - P
• Configurable 8-Channel Input MUX:
  • Single-Channel or Sequential Multi-Channel Sampling
• Input Channel Bandwidth: 500 MHz
• Output Data Format:
  • Parallel CMOS, DDR LVDS
  • Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Built-In ADC Linearity Calibration Algorithms:
  • Harmonic Distortion Correction (HDC)
  • DAC Noise Cancellation (DNC)
  • Dynamic Element Matching (DEM)
  • Flash Error Calibration
• Digital Signal Post-Processing (DSPP) Options:
  • Decimation filters for improved SNR
  • Fractional Delay Recovery (FDR) for timedelay corrections in multi-channel operations
  • Phase, Offset and Gain adjust of individual channels
  • Digital Down-Conversion (DDC)
  • Continuous wave beamforming for octalchannel mode
• Serial Peripheral Interface (SPI)
• Auto Sync Mode to synchronize multiple devices to the same clock
• TFBGA-121 Package
  • Dimension: 8 mm×8 mm×1.08 mm
  • Includes embedded decoupling capacitors for reference pins and bandgap output pin
• AEC-Q100 Qualified (Automotive Applications)
  • Temperature Grade 1: -40℃ to +125℃

• Communication Instruments
• Microwave Digital Radio
• Lidar and Radar
• High-Speed Test Equipment
• Ultrasound and Sonar Imaging
• Scanners and Low-Power Portable Instruments
• Industrial and Consumer Data Acquisition Systems