LCSC Electronics logoLCSC Electronics svg logo
Accedi
USD
Carrello
NXP MPC8248CVRMIBA557 product image
Immagini a scopo illustrativo

NXP MPC8248CVRMIBA557

Produttore
NXP
Cod. Prod.
MPC8248CVRMIBA557
Cod. LCSC
C6909340
Imballo
PBGA-516(27x27)
Numero Cliente
Attr. chiave
PBGA-516(27x27) Microcontrollers
Scheda TecnicaNXP MPC8248CVRMIBA557
Garanzia su ogni ordine
100% Autentico · Reso o Sostituzione entro 30 Giorni
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 3.0265$ 3.03
200+$ 1.2079$ 241.58
500+$ 1.167$ 583.50
1,000+$ 1.1473$ 1147.30
Package Standard1/Full Bag
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProduttoreNXP
ImballoPBGA-516(27x27)
Aiuto & FeedbackMostra prodotti simili (0) >

Caratteristiche

Traduzione AI
  • Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 266–400 MHz
  • Separate 16 KB data and instruction caches:
    • Four-way set associative Physically addressed
    • LRU replacement algorithm
  • Power Architecture -compliant memory management unit (MMU)
  • Common on-chip processor (COP) test interface
  • Supports bus snooping for cache coherency
  • Floating-point unit (FPU) supports floating-point arithmetic
  • Support for cache locking
  • Low-power consumption
  • Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
  • Separate PLLs for G2_LE core and for the communications processor module (CPM)
    • G2_LE core and CPM can run at different frequencies for power/performance optimization
    • Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 7:1, 8:1
    • Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
  • 64-bit data and 32-bit address 60x bus
    • Bus supports multiple master designs—up to two external masters
    • Supports single transfers and burst transfers
    • 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
  • 60x-to-PCI bridge
    • Programmable host bridge and agent
    • 32-bit data bus, 66 MHz, 3.3 V
    • Synchronous and asynchronous 60x and PCI clock modes
    • All internal address space available to external PCI host DMA for memory block transfers
    • PCI-to-60x address remapping
  • System interface unit (SIU)
  • Clock synthesizer
  • Reset controller
  • Real-time clock (RTC) register
  • Periodic interrupt timer
  • Hardware bus monitor and software watchdog timer
  • IEEE 1149.1 JTAG test access port
  • Eight bank memory controller
    • Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other user-definable peripherals
    • Byte write enables
    • 32-bit address decodes with programmable bank size
    • Three user-programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine
    • Byte selects for 64-bit bus width (60x)
    • Dedicated interface logic for SDRAM
  • Disable CPU mode
  • Integrated security engine (SEC) (MPC8272 and MPC8248 only)
    • Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms in hardware
  • Communications processor module (CPM)
    • Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals
    • Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port RAM size is 16 KB plus 4 KB dedicated instruction RAM.)
    • Microcode tracing capabilities
    • Eight CPM trap registers
  • Universal serial bus (USB) controller
    • Supports USB 2.0 full/low rate compatible
    • USB host mode
      • Supports control, bulk, interrupt, and isochronous data transfers
      • CRC16 generation and checking
      • NRZI encoding/decoding with bit stuffing
      • Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub.
      • Flexible data buffers with multiple buffers per frame
      • Supports local loopback mode for diagnostics (12 Mbps only)
    • Supports USB slave mode
      • Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
      • CRC16 generation and checking
      • CRC5 checking
      • NRZI encoding/decoding with bit stuffing
      • 12- or 1.5-Mbps data rate
      • Flexible data buffers with multiple buffers per frame
      • Automatic retransmission upon transmit error
    • Serial DMA channels for receive and transmit on all serial channels
    • Parallel I/O registers with open-drain and interrupt capability
    • Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
    • Two fast communication controllers (FCCs) supporting the following protocols:
      • 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII)
        • Transparent
        • HDLC—up to T3 rates (clear channel)
      • One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155 Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64-K external connections