Infineon CY9BFD18SPMC-GK7FKCGE1

The CY9BD10T series is a highly integrated 32-bit microcontroller designed for embedded control applications requiring high performance and cost competitiveness. Based on the Arm® Cortex®-M3 processor, this series integrates on-chip Flash and SRAM, and features a rich set of peripherals including motor control timers, ADC, and multiple communication interfaces (USB, CAN, UART, CSIO, I2C, LIN, and Ethernet MAC). Products described in this datasheet are classified under the TYPE 2 product category in the "FM3 Family Peripheral Manual."

• 32-bit Arm® Cortex®-M3 core, processor revision r2p1, operating frequency up to 144 MHz
• Integrated MPU for enhanced embedded system reliability
• Integrated NVIC supporting 1 NMI and 48 peripheral interrupts with 16 priority levels
• Integrated 24-bit SysTick timer for OS task management
• On-chip flash up to 1 MB with built-in flash accelerator featuring 16 KB trace buffer, supporting code protection security
• On-chip SRAM up to 128 KB total, consisting of two independent SRAMs (SRAM0 and SRAM1), each up to 64 KB
• USB interface up to 2 channels, supporting device and host functions, USB 2.0 full-speed mode
• USB device supports up to 6 endpoints: EP0 for control transfers, EP1–5 for bulk, interrupt, or isochronous transfers with double buffering
• USB host supports USB 2.0 full-speed/low-speed mode, bulk/interrupt/isochronous transfers, automatic connection detection, automatic token/handshake packet handling, maximum 256-byte packet length, and remote wakeup
• CAN interface up to 2 channels, compliant with CAN specification 2.0A/B, maximum bit rate 1 Mbps, 32 message buffers
• Ethernet MAC up to 2 channels, IEEE 802.3 compliant, 10 Mbps and 100 Mbps data rates, MII/RMII interface for external PHY, full-duplex and half-duplex modes, Magic Packet wakeup, dedicated descriptor-based DMA controller, 2 KB TX FIFO and 2 KB RX FIFO, IEEE 1588-2008 compliant
• Multi-function serial interface up to 8 channels: 4 channels with 16-stage × 9-bit FIFO, 4 channels without FIFO; each channel independently selectable as UART, CSIO, or LIN mode
• UART mode: full-duplex double-buffered, selectable parity, dedicated baud rate generator, external clock support, hardware flow control (channel 4 only), multiple error detection
• CSIO mode: full-duplex double-buffered, dedicated baud rate generator, overrun error detection
• LIN mode: LIN protocol Rev. 2.1, full-duplex double-buffered, master/slave mode, LIN break field and delimiter generation, multiple error detection
• I2C interface: standard mode (up to 100 kbps) and fast mode (up to 400 kbps)
• External bus interface: supports SRAM, NOR, and NAND flash devices, up to 8 chip selects, 8-bit or 16-bit data width, up to 25-bit address, 256 MB maximum address space, address/data multiplexing, external RDY input
• DMA controller: 8 independent channels, dedicated bus independent of CPU enabling concurrent CPU/DMA operation, transfers initiated by software or on-chip peripheral requests, 32-bit address space, block/burst/demand transfer modes, byte/halfword/word data types
• ADC: up to 32 channels, 12-bit SAR type, 3 built-in units, conversion time 1.0 μs at 5V supply, two-level priority conversion and scan conversion modes, built-in FIFO for conversion data storage