TI SN74LS674DW

The LS673 is a 16-bit serial-in, serial-out shift register with a 16-bit parallel-output storage register. The SN54LS673 and SN74LS673 integrate a 16-bit shift register and a 16-bit storage register in a single 24-pin package. The shift register features a three-state input/output (SER/Q15) port that allows serial input and/or data readback. The storage register is connected to the shift register in a parallel data loop and can be asynchronously cleared by pulling the storage clear input low. The storage register can be parallel-loaded with shift register data and provides the shift register state via parallel outputs. The shift register can be parallel-loaded with storage register data on command. A high logic level applied to the chip select (CS) input disables both the shift register clock and the storage register clock, and places SER/Q15 in a high-impedance state. Chip select does not disable the storage clear function. Care must be taken to prevent false clocking of the shift register or storage register through the CS input. The shift clock should be held low during CS low-to-high transitions; the storage clock should be held low during CS high-to-low transitions. The LS674 is a 16-bit parallel-in, serial-out shift register. The SN54LS674 and SN74LS674 feature a three-state input/output (SER/Q15) port for serial data input or shift register word readback in a recirculating loop. The device supports four basic operating modes: 1) Hold (do nothing); 2) Write (serial write via I/O); 3) Read (serial read); 4) Load (parallel load via data inputs). Low-to-high transitions on the chip select input are permitted only when the clock input is low, to prevent false clock triggering.

• LS673 for serial-to-parallel conversion
• LS674 for parallel-to-serial conversion
• LS673 integrates 16-bit shift register and 16-bit storage register in a single 24-pin package
• LS673 shift register with tri-state I/O (SER/Q15) port for serial input and/or data readback
• LS673 storage register supports asynchronous clear
• LS673 storage register parallel-loadable from shift register data, with shift register status available via parallel outputs
• LS673 shift register on-command parallel loadable from storage register data
• Chip select input disables shift register clock and storage register clock, placing SER/Q15 in high-impedance state
• LS674 supports four basic operating modes: hold, serial write, serial read, and parallel load