TI SN74ALVC162334DGVR

This is a 16-bit universal bus driver designed for 1.65 V to 3.6 V VCC operating environments. The output enable (OE) input controls data flow from port A to port Y. When the latch enable (LE) input is low, the device operates in transparent mode. When LE is high, port A data is latched if the clock (CLK) input remains at a high or low logic level; if LE is high, port A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in a high-impedance state. The outputs are designed to sink up to 12 mA, with a built-in equivalent 26-Ω series resistor to reduce overshoot and undershoot. To ensure the device remains in a high-impedance state during power-up or power-down, OE should be connected to VCC through a pull-up resistor; the minimum resistor value is determined by the sink current capability of the driver.

• Member of Texas Instruments Widebus™ family
• For PC100 registered DIMMs
• Operating voltage range: 1.65 V to 3.6 V
• Maximum tpd of 3.8 ns at 3.3 V
• Output drive of ±12 mA at 3.3 V
• Built-in equivalent 26-Ω series resistor on output ports — no external resistor required
• Designed to JEDEC 168-pin and 200-pin SDRAM buffered DIMM specifications
• Latch-up performance exceeds 250 mA per JESD 17
• ESD protection exceeds JESD 22 requirements
• 2000-V Human Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged Device Model (C101)

• PC100 Registered DIMM