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RENESAS ISL6532ACRZ-TK

Fabricante
Cód. da peça
ISL6532ACRZ-TK
Nº LCSC
C2156187
Emb.
QFN-28-EP(6x6)
Número do Cliente
Atrib. princ.
QFN-28-EP(6x6) Power Management - Specialized RoHS
Folha de DadosRENESAS ISL6532ACRZ-TK
Garantia em cada pedido
100% Autêntico · Devolução ou Substituição em 30 Dias
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Mínimo: 1Múltiplo: 1Unidade de venda: Piece
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Qtd.Preço unit.(Apenas para referência)Valor total
1+$ 4.8082$ 4.81
200+$ 1.8616$ 372.32
500+$ 1.7952$ 897.60
1,000+$ 1.7628$ 1762.80
Encapsulamento Padrão1000/Full Reel
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Especificações do Produto

Tudo
TipoDescrição
CategoriaIntegrated Circuits (ICs)/Power Management (PMIC)/Power Management - Specialized
FabricanteRENESAS
Emb.QFN-28-EP(6x6)
FeaturesAdjustable current limiting;Hiccup current limiting;Overcurrent Protection;Built-in LDO regulator;Operating status indication
Operating Temperature0℃~+70℃
Interface-
Voltage - Supply-
Output Voltage-

Descrição

Tradução por IA

The ISL6532A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller and integrated LDO to supply V_DDQ with high current during S0/S1 states and standby current during S3 state. During S0/S1 state, a fully integrated sink - source regulator generates an accurate (V_DDQ / 2) high current V_TT voltage without the need for a negative supply. A buffered version of the V_DDQ / 2 reference is provided as VREF. An LDO controller is also integrated for AGP core voltage regulation. The switching PWM controller drives two N - Channel MOSFETs in a synchronous - rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. Both the switching regulator and standby LDO provide a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user - adjustable by means of external resistors down to 0.8 V. Switching memory core output between the PWM regulator and the standby LDO during state transitions is accomplished smoothly via the internal ACPI control circuitry. The NCH signal provides synchronized switching of a backfeed blocking switch during the transitions eliminating the need to route 5V Dual to the memory supply. An integrated soft - start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the PGOOD signal indicates V_TT is within spec and operational. Each output is monitored for under and overvoltage events. The switching regulator has overcurrent protection. Thermal shutdown is integrated.

Recursos

Tradução por IA
  • Generates 3 Regulated Voltages - Synchronous Buck PWM Controller with Standby LDO - 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference - Glitch - free Transitions During State Changes - LDO Regulator for 1.5V Video and Core voltage
  • ACPI Compliant Sleep State Control
  • Integrated VREF Buffer
  • PWM Controller Drives Low Cost N - Channel MOSFETs
  • 250kHz Constant Frequency Operation
  • Tight Output Voltage Regulation - All Outputs: ±2% Over - Temperature
  • 5V or 3.3V Down Conversion
  • Fully - Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
  • Pb - free Available (RoHS Compliant)

Aplicações

Tradução por IA
  • Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs
  • Graphics Cards - GPU and Memory Supplies
  • ASIC Power Supplies
  • Embedded Processor and I/O Supplies
  • DSP Supplies