GSI Technology GS8160Z36DGT-333IV

GS8160Z18/36DGT-xxxV is an 18Mbit synchronous SRAM. NBT SRAMs, such as ZBT, NtRAM, NoBL, or other pipelined read/double-latency write or flow-through read/single-latency write SRAMs, eliminate the need to insert deselect cycles when switching from read to write cycles, allowing full utilization of all available bus bandwidth. As a synchronous device, addresses, data inputs, and read/write control inputs are captured on the rising edge of the input clock. The burst order control pin must be connected to a power rail for proper operation. Asynchronous inputs include sleep mode enable and output enable. Output enable can be used to override the synchronous control of the output drivers and disable the RAM output drivers at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates the complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. GS8160Z18/36DGT-xxxV is user-configurable to operate in either pipelined or flow-through mode. Operating as a pipelined synchronous device means that in addition to the rising-edge-triggered registers that capture input signals, the device also contains a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle, then released to the output drivers on the next rising clock edge.

• NBT functionality enables zero wait-state read/write bus utilization; fully pin-compatible with pipelined and flow-through NtRAM, NoBL, and ZBT SRAM
• 1.8V or 2.5V core supply voltage
• 1.8V or 2.5V I/O supply voltage
• User-configurable pipeline and flow-through modes
• LBO pin for linear or interleaved burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb, and 144Mb devices
• Byte write operation
• 3 chip enable signals for depth expansion
• ZZ pin for automatic power-down
• RoHS-compliant 100-pin TQFP package available