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EDA 모델EasyEDA
MICROCHIP dsPIC33CK64MP203-E/M5
| 제조업체 | |
| 제조사 품번 | dsPIC33CK64MP203-E/M5 |
| LCSC 번호 | C638741 |
| 포장 | UQFN-36-EP(5x5) |
| 고객 번호 | |
| 주요 제원 | UQFN-36-EP(5x5) Microcontrollers RoHS |
| 데이터시트 | MICROCHIP dsPIC33CK64MP203-E/M5 |
| RoHS 준수 | 2개 문서 이용 가능 |
제품 사양
전체
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| 제조업체 | MICROCHIP | |
| 포장 | UQFN-36-EP(5x5) | |
| Operating Temperature | -40℃~+125℃ |
| 타입 | 설명 | |
|---|---|---|
| 포장 | UQFN-36-EP(5x5) | |
| Operating Temperature | -40℃~+125℃ |
도움말 및 피드백유사 제품 보기 (0) >
주요 특징
AI 번역
- 32 - 256 Kbytes of Program Flash with ECC and 8 - 24K RAM
- Fast 6 - Cycle Divide
- LiveUpdate
- Code Efficient (C and Assembly) Architecture
- 40 - Bit Wide Accumulators
- Single - Cycle (MAC/MPY) with Dual Data Fetch
- Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
- 32 - Bit Multiply Support
- Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling
- Zero Overhead Looping
- RAM Memory Built - In Self - Test (MBIST)
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Reference Clock Output
- Fail - Safe Clock Monitor (FSCM)
- Fast Wake - up and Start - up
- Backup Internal Oscillator
- Low - Power Management Modes (Sleep, Idle, Doze)
- Integrated Power - on Reset and Brown - out Re
- Eight PWM Pairs
- Up to 250 ps PWM Resolution
- Dead Time for Rising and Falling Edges
- Dead - Time Compensation
- Clock Chopping for High - Frequency Operation
- Fault and Current Limit Inputs
- Flexible Trigger Configuration for ADC Triggering
- One General Purpose Timer
- Peripheral Trigger Generator (PTG): Up to 15 trigger sources to other peripheral modules, CPU independent state machine - based instruction sequencer
- Nine MCCP/SCCP modules which Include Timer, Capture/Compare and PWM: One MCCP Eight SCCPs, 16 or 32 - bit time base, 16 or 32 - bit capture, 4 - deep capture buffer
- Fully Asynchronous Operation, Available in Sleep Modes
- High - Speed ADC module: 12 - bit with two dedicated SAR ADC cores and one shared SAR ADC core, Configurable resolution (up to 12 - bit) for each ADC core, Up to 3.5 Msps conversion rate per channel at 12 - bit resolution, Up to 24 input channels, Dedicated result buffer for each analog channel, Flexible and independent ADC trigger sources, Four digital comparators, Four oversampling filters for increased resolution
- Up to Three Analog Comparators: 15 ns analog comparator
- Up to Three Op Amps
- Three 12 - Bit DACs: Hardware slope compensation
- Three Protocol UARTs with Automated Protocol Handling Support for: LIN 2.2, DMX, IrDA
- 3 Four - Wire SPI/I²S modules
- CAN Flexible Data (FD) module
- Three I²C modules with SMBus Support
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC)
- Two SENT modules
- Parallel Master Port (PMP)
- Four DMA Channels
- In - Circuit and In - Application Programming and Debugging
- Three Complex, Five Simple Breakpoints
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run - Time Watch
- Clock Monitor System with Backup Oscillator
- DMT (Deadman Timer)
- ECC (Error Correcting Code)
- WDT (Watchdog Timer)
- CodeGuard Security
- CRC (Cyclic Redundancy Check)
- Flash OTP by ICSP Write Inhibit
- Two - Speed Start - up
- Fail - Safe Clock Monitoring (FSCM)
- Backup FRC (BFRC)
- Capless Internal Voltage Regulator
- Virtual Pins for Redundancy and Monitoring
- AEC - Q100 REV - H (Grade 1: - 40℃ to + 125℃) Compliant
- AEC - Q100 REV - H (Grade 0: - 40℃ to + 150℃) Compliant
모든 주문 보장
100% 정품 · 30일 반품 또는 교환
품절
재입고 알림
최소값: 1배수: 1판매 단위: Piece
BOM 목록에 추가
| 수량 | 단가(참고용) | 총액 |
|---|---|---|
| 1+ | $ 5.7835 | $ 5.78 |
| 200+ | $ 2.2391 | $ 447.82 |
| 500+ | $ 2.1601 | $ 1080.05 |
| 1,000+ | $ 2.1206 | $ 2120.60 |
표준 패키지73/Full Tube | ||
수량이 많을수록 더 좋은 가격?
$
제품 사양
전체
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| 제조업체 | MICROCHIP | |
| 포장 | UQFN-36-EP(5x5) | |
| Operating Temperature | -40℃~+125℃ |
| 타입 | 설명 | |
|---|---|---|
| 포장 | UQFN-36-EP(5x5) | |
| Operating Temperature | -40℃~+125℃ |
도움말 및 피드백유사 제품 보기 (0) >
주요 특징
AI 번역
- 32 - 256 Kbytes of Program Flash with ECC and 8 - 24K RAM
- Fast 6 - Cycle Divide
- LiveUpdate
- Code Efficient (C and Assembly) Architecture
- 40 - Bit Wide Accumulators
- Single - Cycle (MAC/MPY) with Dual Data Fetch
- Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
- 32 - Bit Multiply Support
- Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling
- Zero Overhead Looping
- RAM Memory Built - In Self - Test (MBIST)
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Reference Clock Output
- Fail - Safe Clock Monitor (FSCM)
- Fast Wake - up and Start - up
- Backup Internal Oscillator
- Low - Power Management Modes (Sleep, Idle, Doze)
- Integrated Power - on Reset and Brown - out Re
- Eight PWM Pairs
- Up to 250 ps PWM Resolution
- Dead Time for Rising and Falling Edges
- Dead - Time Compensation
- Clock Chopping for High - Frequency Operation
- Fault and Current Limit Inputs
- Flexible Trigger Configuration for ADC Triggering
- One General Purpose Timer
- Peripheral Trigger Generator (PTG): Up to 15 trigger sources to other peripheral modules, CPU independent state machine - based instruction sequencer
- Nine MCCP/SCCP modules which Include Timer, Capture/Compare and PWM: One MCCP Eight SCCPs, 16 or 32 - bit time base, 16 or 32 - bit capture, 4 - deep capture buffer
- Fully Asynchronous Operation, Available in Sleep Modes
- High - Speed ADC module: 12 - bit with two dedicated SAR ADC cores and one shared SAR ADC core, Configurable resolution (up to 12 - bit) for each ADC core, Up to 3.5 Msps conversion rate per channel at 12 - bit resolution, Up to 24 input channels, Dedicated result buffer for each analog channel, Flexible and independent ADC trigger sources, Four digital comparators, Four oversampling filters for increased resolution
- Up to Three Analog Comparators: 15 ns analog comparator
- Up to Three Op Amps
- Three 12 - Bit DACs: Hardware slope compensation
- Three Protocol UARTs with Automated Protocol Handling Support for: LIN 2.2, DMX, IrDA
- 3 Four - Wire SPI/I²S modules
- CAN Flexible Data (FD) module
- Three I²C modules with SMBus Support
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC)
- Two SENT modules
- Parallel Master Port (PMP)
- Four DMA Channels
- In - Circuit and In - Application Programming and Debugging
- Three Complex, Five Simple Breakpoints
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run - Time Watch
- Clock Monitor System with Backup Oscillator
- DMT (Deadman Timer)
- ECC (Error Correcting Code)
- WDT (Watchdog Timer)
- CodeGuard Security
- CRC (Cyclic Redundancy Check)
- Flash OTP by ICSP Write Inhibit
- Two - Speed Start - up
- Fail - Safe Clock Monitoring (FSCM)
- Backup FRC (BFRC)
- Capless Internal Voltage Regulator
- Virtual Pins for Redundancy and Monitoring
- AEC - Q100 REV - H (Grade 1: - 40℃ to + 125℃) Compliant
- AEC - Q100 REV - H (Grade 0: - 40℃ to + 150℃) Compliant
C638741 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| 타입 | 세부사항 |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |