- Pinbelegung
- Footprint
Abbildung ähnlich
EDA-ModelleEasyEDA
Intel/Altera EP3C25E144I7N
| Hersteller | |
| Herst.-Teilenr. | EP3C25E144I7N |
| LCSC-Nr. | C568974 |
| Verp. | LQFP-144-EP(20x20) |
| Kundennummer | |
| Hauptmerkm. | 82 24624 1539 LQFP-144-EP(20x20) FPGAs (Field Programmable Gate Array) RoHS |
| Datenblatt | Intel/Altera EP3C25E144I7N |
| RoHS-Konformität | 1 Dokumente verfügbar |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Hersteller | Intel/Altera | |
| Verp. | LQFP-144-EP(20x20) | |
| Total RAM capacity | 608256bit | |
| Number of I/O | 82 | |
| Number of Logic Elements/Blocks | 24624 | |
| Number of LAB/CLBs | 1539 | |
| Programmable Type | - |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Hersteller | Intel/Altera | |
| Verp. | LQFP-144-EP(20x20) | |
| Total RAM capacity | 608256bit |
| Typ | Beschreibung | |
|---|---|---|
| Number of I/O | 82 | |
| Number of Logic Elements/Blocks | 24624 | |
| Number of LAB/CLBs | 1539 | |
| Programmable Type | - |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- Lowest Power FPGAs
- Design Security Feature
- Increased System Integration
- LE Features
- Control Signals
- Parity Bit Support
- Byte Enable Support
- Packed Mode Support
- Address Clock Enable Support
- Mixed-Width Support
- Asynchronous Clear
- Memory Modes
- Clocking Modes
- Embedded Multiplier Block Overview
- Architecture
- Operational Modes
- Clock Networks
- GCLK Network
- Clock Control Block
- GCLK Network Clock Source Generation
- GCLK Network Power Down
- clkena Signals
- Cyclone III Device Family PLL Hardware Overview
- External Clock Outputs
- Clock Feedback Modes
- Hardware Features
- Clock Multiplication and Division
- Post-Scale Counter Cascading
- Programmable Duty Cycle
- PLL Control Signals
- Clock Switchover
- Automatic Clock Switchover
- Manual Override
- Manual Clock Switchover
- Guidelines
- Programmable Bandwidth
- Phase Shift Implementation
- PLL Cascading
- PLL Reconfiguration
- PLL Reconfiguration Hardware Implementation
- Post-Scale Counters (C0 to C4)
- Scan Chain Description
- Charge Pump and Loop Filter
- Bypassing PLL Counter
- Dynamic Phase Shifting
- Spread-Spectrum Clocking
- Cyclone III Device Family I/O Elements
- I/O Element Features
- Programmable Current Strength
- Slew Rate Control
- Open-Drain Output
- Bus Hold
- Programmable Pull-Up Resistor
- Programmable Delay
- PCI-Clamp Diode
- LVDS Transmitter Programmable Pre-Emphasis
- OCT Support
- On-Chip Series Termination with Calibration
- On-Chip Series Termination Without Calibration
- I/O Standards
- Termination Scheme for I/O Standards
- Voltage-Referenced I/O Standard Termination
- Differential I/O Standard Termination
- I/O Banks
- High-Speed Differential Interfaces
- External Memory Interfacing
- Pad Placement and DC Guidelines
- Pad Placement
- DC Guidelines
- High-Speed I/O Interface
- High-Speed I/O Standards Support
- LVDS I/O Standard Support in the Cyclone III Device Family
- Designing with LVDS
- BLVDS I/O Standard Support in the Cyclone III Device Family
- Designing with BLVDS
- RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family
- Designing with RSDS, Mini-LVDS, and PPDS
- LVPECL I/O Support in the Cyclone III Device Family
- Differential SSTL I/O Standard Support in the Cyclone III Device Family
- Differential HSTL I/O Standard Support in the Cyclone III Device Family
- True Output Buffer Feature
- Programmable Pre-Emphasis
- High-Speed I/O Timing
- Design Guidelines
- Differential Pad Placement Guidelines
- Board Design Considerations
- Software Overview
- Cyclone III Device Family Memory Interfaces Pin Support
- Data and Data Clock/Strobe Pins
- Optional Parity, DM, and Error Correction Coding Pins
- Address and Control/Command Pins
- Memory Clock Pins
- Cyclone III Device Family Memory Interfaces Features
- DDR Input Registers
- DDR Output Registers
- OCT
- PLL
Garantie auf jede Bestellung
100% Authentisch · 30-Tage-Rückgabe oder -Umtausch
Vorrätig: 3
3 Ab Lager, sofort versandfertig
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
| Stk. | E-Preis | Gesamtbetrag |
|---|---|---|
| 1+ | $ 118.0269 | $ 118.03 |
| 10+ | $ 105.6523 | $ 1056.52 |
Standardgehäuse60/Full Tray | ||
Besserer Preis bei größerer Menge?
$
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Hersteller | Intel/Altera | |
| Verp. | LQFP-144-EP(20x20) | |
| Total RAM capacity | 608256bit | |
| Number of I/O | 82 | |
| Number of Logic Elements/Blocks | 24624 | |
| Number of LAB/CLBs | 1539 | |
| Programmable Type | - |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Hersteller | Intel/Altera | |
| Verp. | LQFP-144-EP(20x20) | |
| Total RAM capacity | 608256bit |
| Typ | Beschreibung | |
|---|---|---|
| Number of I/O | 82 | |
| Number of Logic Elements/Blocks | 24624 | |
| Number of LAB/CLBs | 1539 | |
| Programmable Type | - |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- Lowest Power FPGAs
- Design Security Feature
- Increased System Integration
- LE Features
- Control Signals
- Parity Bit Support
- Byte Enable Support
- Packed Mode Support
- Address Clock Enable Support
- Mixed-Width Support
- Asynchronous Clear
- Memory Modes
- Clocking Modes
- Embedded Multiplier Block Overview
- Architecture
- Operational Modes
- Clock Networks
- GCLK Network
- Clock Control Block
- GCLK Network Clock Source Generation
- GCLK Network Power Down
- clkena Signals
- Cyclone III Device Family PLL Hardware Overview
- External Clock Outputs
- Clock Feedback Modes
- Hardware Features
- Clock Multiplication and Division
- Post-Scale Counter Cascading
- Programmable Duty Cycle
- PLL Control Signals
- Clock Switchover
- Automatic Clock Switchover
- Manual Override
- Manual Clock Switchover
- Guidelines
- Programmable Bandwidth
- Phase Shift Implementation
- PLL Cascading
- PLL Reconfiguration
- PLL Reconfiguration Hardware Implementation
- Post-Scale Counters (C0 to C4)
- Scan Chain Description
- Charge Pump and Loop Filter
- Bypassing PLL Counter
- Dynamic Phase Shifting
- Spread-Spectrum Clocking
- Cyclone III Device Family I/O Elements
- I/O Element Features
- Programmable Current Strength
- Slew Rate Control
- Open-Drain Output
- Bus Hold
- Programmable Pull-Up Resistor
- Programmable Delay
- PCI-Clamp Diode
- LVDS Transmitter Programmable Pre-Emphasis
- OCT Support
- On-Chip Series Termination with Calibration
- On-Chip Series Termination Without Calibration
- I/O Standards
- Termination Scheme for I/O Standards
- Voltage-Referenced I/O Standard Termination
- Differential I/O Standard Termination
- I/O Banks
- High-Speed Differential Interfaces
- External Memory Interfacing
- Pad Placement and DC Guidelines
- Pad Placement
- DC Guidelines
- High-Speed I/O Interface
- High-Speed I/O Standards Support
- LVDS I/O Standard Support in the Cyclone III Device Family
- Designing with LVDS
- BLVDS I/O Standard Support in the Cyclone III Device Family
- Designing with BLVDS
- RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family
- Designing with RSDS, Mini-LVDS, and PPDS
- LVPECL I/O Support in the Cyclone III Device Family
- Differential SSTL I/O Standard Support in the Cyclone III Device Family
- Differential HSTL I/O Standard Support in the Cyclone III Device Family
- True Output Buffer Feature
- Programmable Pre-Emphasis
- High-Speed I/O Timing
- Design Guidelines
- Differential Pad Placement Guidelines
- Board Design Considerations
- Software Overview
- Cyclone III Device Family Memory Interfaces Pin Support
- Data and Data Clock/Strobe Pins
- Optional Parity, DM, and Error Correction Coding Pins
- Address and Control/Command Pins
- Memory Clock Pins
- Cyclone III Device Family Memory Interfaces Features
- DDR Input Registers
- DDR Output Registers
- OCT
- PLL
C568974 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Typ | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Typ | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |