Carica BOM

Immagini a scopo illustrativo

Modelli EDAEasyEDA

TI SNJ54HC4040J

Produttore	TI
Cod. Prod.	SNJ54HC4040J
Cod. LCSC	C5218016
Imballo	CDIP-16
Numero Cliente
Attr. chiave	Falling Edge CDIP-16 Counters, Dividers RoHS
Scheda Tecnica	TI SNJ54HC4040J
Conformità RoHS	2 documenti disponibili

Specifiche del Prodotto

Tutto

Tipo	Descrizione
Categoria	Integrated Circuits (ICs)/Logic/Counters, Dividers
Produttore	TI
Imballo	CDIP-16
Logic Family	74HC
Voltage - Supply	2V~6V
Direction	-
Trigger Type	Falling Edge
Timing	Asynchronous
Operating Temperature	-55℃~+125℃
Reset	Asynchronous
Number of Elements	-
Propagation Delay	26ns@6V,50pF
Count Rate	-
Features	Reset function

Traduzione AI

Wide operating voltage range: 2V to 6V
Output drives up to 10 LSTTL loads
Low power consumption, ICC max = 80 μA
tpd typical = 12 ns
±4 mA output drive (at 5V)
Low input current, max 1 μA
The 'HC4040 device is a 12-stage asynchronous binary counter with outputs available from all stages. Drive the clear (CLR) input high to asynchronously clear the counter and reset all outputs low. The count advances on the high-to-low transition of the clock (CLK) input.

Traduzione AI

Garanzia su ogni ordine

100% Autentico · Reso o Sostituzione entro 30 Giorni

Esaurito

Avvisami

Minimo: 1Multiplo: 1Unità di vendita: Piece

Aggiungi alla Lista BOM

Prezzo migliore per quantità maggiore?

Tutto

Tipo	Descrizione
Categoria	Integrated Circuits (ICs)/Logic/Counters, Dividers
Produttore	TI
Imballo	CDIP-16
Logic Family	74HC
Voltage - Supply	2V~6V
Direction	-
Trigger Type	Falling Edge
Timing	Asynchronous
Operating Temperature	-55℃~+125℃
Reset	Asynchronous
Number of Elements	-
Propagation Delay	26ns@6V,50pF
Count Rate	-
Features	Reset function

Traduzione AI

Wide operating voltage range: 2V to 6V
Output drives up to 10 LSTTL loads
Low power consumption, ICC max = 80 μA
tpd typical = 12 ns
±4 mA output drive (at 5V)
Low input current, max 1 μA
The 'HC4040 device is a 12-stage asynchronous binary counter with outputs available from all stages. Drive the clear (CLR) input high to asynchronously clear the counter and reset all outputs low. The count advances on the high-to-low transition of the clock (CLK) input.

Traduzione AI