TI SNJ54LS139AJ

These Schottky-clamped TTL MSl circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with highspeed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The circuit comprises two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS139A and SN54S139 are characterized for operation range of -55°C to 125°C. The SN74LS139A and SN74S139A are characterized for operation from 0°C to 70°C.

• Designed for high-speed applications with Schottky clamping for high performance
• Integrates two fully independent 2-line-to-4-line decoders/demultiplexers
• Active-low enable inputs usable as data lines in demultiplexing applications
• All inputs fully buffered — each input presents only one normalized load to the driving circuit
• All inputs feature high-performance Schottky diode clamping to suppress line ringing and simplify system design
• SN54LS139A, SN54S139: operating temperature range -55°C to 125°C
• SN74LS139A, SN74S139A: operating temperature range 0°C to 70°C
• Storage temperature range: -65°C to 150°C
• Maximum rated supply voltage VCC: 7V
• LS139A max input voltage: 7V; 54S139, 74S139A max input voltage: 5.5V

• High-performance memory decoding
• Data routing and transmission
• For use with high-speed memory — minimizes system decoding impact with negligible effective system delay