Infineon/CYPRESS CY7C1333-66AC

CY7C1333 is a 3.3V, 64K×32 synchronous flow-through burst SRAM designed to support unlimited consecutive read and write operations without wait states. The device incorporates advanced No Bus Latency (NoBL™) logic, enabling data transfer every clock cycle for continuous read/write operation. This feature significantly improves data throughput through the SRAM, making it especially suitable for systems requiring frequent write-to-read transitions. The CY7C1333 is pin and functionally compatible with the ZBT SRAM MT55L64L32F. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by a Clock Enable (CEN) signal; when CEN is deasserted, operation is suspended and the previous clock cycle is extended. The maximum access latency from the clock rising edge is 12.0 ns (66-MHz device). Write operations are controlled by four Byte Write Selects (BWS[0:3]) and a Write Enable (WE) input. All write operations are performed through an on-chip synchronous self-timed write circuit. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) facilitate memory bank selection and output tri-state control. To avoid bus contention, the output drivers synchronously enter tri-state during the data portion of a write sequence.

• Pin-compatible with ZBT™ device MT55L64L32F, functionally equivalent
• Supports 66 MHz bus operation, zero wait states, data transfer every clock cycle
• Internal self-timed output buffer control, OE not required
• Registered inputs for flow-through operation
• Byte write capability
• 64K×32 common I/O architecture
• Single 3.3V supply
• Fast clock-to-output time — 12.0 ns (66 MHz device) — 14.0 ns (50 MHz device)
• Clock enable (CEN) pin for suspending operation
• Synchronous self-timed write operation
• Asynchronous output enable
• JEDEC standard 100-pin TQFP package
• Burst capability — linear or interleaved burst order
• Low (16.5 mW) standby power consumption