Infineon/CYPRESS CYD18S36V18-200BBAXI

The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

The advanced features include the following:

• Built-in deterministic access control to manage address collisions during simultaneous access to the same memory location
• Variable impedance matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance
• Echo clocks to improve data transfer

To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles, before a change in CE0 (overline) or CE1 enables or disables the databus, matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port.

Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally.

Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt (CNTINT) flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset (MRST) are also available.

The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package except the 36-Mbit devices which are offered in 484-ball plastic BGA package.

• True dual port memory enables simultaneous access the shared array from each port
• Synchronous pipelined operation with single data rate (SDR) operation on each port
• SDR interface at 200 MHz
• Up to 28.8 Gbps bandwidth (200 MHzx72-bitx2 ports)
• 1.5 V or 1.8 V core power supply
• IEEE 1149.1 JTAG boundary scan
• Commercial and Industrial temperature
• Selectable pipelined or flow-through mode
• Available in 484-ball PBGA (x 72) and 256-ball FBGA (x 36 and x18) packages