TI ADS41B25IRGZT

The ADS41B25 features an integrated analog input buffer and employs innovative design techniques to achieve high dynamic performance with ultra-low power consumption. The buffered analog input pins deliver consistent performance and input impedance across a wide frequency range, making the device well-suited for multi-carrier, large-bandwidth communications applications such as PA linearization. The device offers digital gain and offset correction; gain options improve SFDR performance at lower full-scale input ranges, and an integrated DC offset correction loop evaluates and eliminates ADC offset. At lower sampling rates, operating power consumption is automatically reduced without any performance degradation. DDR, LVDS, and CMOS digital output interfaces are supported. The DDR LVDS interface enables the use of low-cost receivers at reduced data rates, a low-swing LVDS mode lowers power consumption, and LVDS output buffer drive strength can be increased to support 50Ω differential termination. Programmable gain supports SNR/SFDR trade-off, DC offset correction, and low input clock amplitude operation. The device is housed in a compact QFN-48 package and is specified over the industrial temperature range (−40°C to +85°C).

• Maximum sample rate: 125MSPS
• Ultra-low power consumption:
  • 1.8V analog power: 114mW
  • 3.3V buffer power: 96mW
  • I/O power: 100mW (DDR LVDS)
• High dynamic performance:
  • SNR: 68.3dBFS (at 170MHz)
  • SFDR: 87dBc (at 170MHz)
• Programmable gain for SNR/SFDR trade-off and DC offset correction
• Low input clock amplitude support
• Package: QFN-48 (7mm x 7mm)

• Multi-carrier, wide-bandwidth communication applications such as PA linearization