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onsemi CM2009-02QR product image
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onsemi CM2009-02QR

Fabricante
Cód. da peça
CM2009-02QR
Nº LCSC
C233381
Emb.
QSOP-16-150mil
Número do Cliente
Atrib. princ.
6VC Clamp ESD DIODE QSOP-16-150mil
Folha de Dadosonsemi CM2009-02QR
Conformidade RoHS3 documentos disponíveis
Garantia em cada pedido
100% Autêntico · Devolução ou Substituição em 30 Dias

Especificações do Produto

Tudo
TipoDescrição
CategoriaCircuit Protection/Transient Voltage Suppressors (TVS)/TVS Diodes
Fabricanteonsemi
Emb.QSOP-16-150mil
Clamping Voltage6V
Operating Temperature-40℃~+85℃
Peak Pulse Current (Ipp)-
Peak Pulse Power Dissipation (Ppp)-
Voltage - Breakdown-
Number of ChannelsSeven channels
typeESD
Reverse Leakage Current (Ir)10uA
PolarityBidirectional
Reverse Stand-Off Voltage (Vrwm)-

Descrição

Tradução por IA

The CM2009 connects between a video graphics controller embedded in a PC, graphics adapter card or set top box and the VGA or DVI−I port connector. The CM2009 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low−capacitance current steering diodes. All ESD diodes are designed to safely handle the high current spikes specified by IEC−61000−4−2 Level 4 ±8 kV contact discharge (if C_BYP is present, ±4 kV if not). The ESD protection for the DDC signal pins are designed to prevent “back current” when the device is powered down while connected to a monitor that is powered up. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs to provide design flexibility in multi−supply−voltage environments. Two non−inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V_CC,SYNC, which is typically 5 V. Additionally, each driver has a series termination resistor (R_T) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. There are three versions with different values of R_T to allow termination at typically 65 Ω (CM2009−00) or 15 Ω (CM2009−02). The 15 Ω (CM2009−02) version will typically require two external resistors which can be chosen to exactly match the characteristic impedance of the SYNC lines of the video cable. Two N−channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (V_CC_DDC) should be connected to the supply rail (typically 3.3 V) that supplies power to the transceivers of the DDC controller.

Recursos

Tradução por IA
  • Includes ESD Protection, Level−Shifting, Buffering and Sync Impedance Matching
  • 7 Channels of ESD Protection for all VGA Port Connector Pins Meeting IEC−61000−4−2 Level 4 ESD Requirements (±8 kV Contact Discharge)
  • Very Low Loading Capacitance from ESD Protection Diodes on VIDEO Lines (4 pF Maximum)
  • 5 V Drivers for HSYNC and VSYNC Lines
  • Integrated Impedance Matching Resistors on Sync Lines
  • Bi−directional Level Shifting N−Channel FETs Provided for DDC_CLK & DDC_DATA Channels
  • Backdrive Protection on DDC Lines
  • Compact 16−Lead QSOP Package
  • These Devices are Pb−Free and are RoHS Compliant

Aplicações

Tradução por IA
  • VGA and DVI−I Ports in Desktop and Notebook PCs
  • VGA and DVI−I Ports in Graphics Cards
  • VGA and DVI−I Ports in Set Top Boxes