AMD/XILINX XCR3512XL-10FTG256I
| Produttore | |
| Cod. Prod. | XCR3512XL-10FTG256I |
| Cod. LCSC | C1556485 |
| Imballo | FTBGA-256 |
| Numero Cliente | |
| Attr. chiave | FTBGA-256 FPGAs (Field Programmable Gate Array) RoHS |
| Scheda Tecnica | AMD/XILINX XCR3512XL-10FTG256I |
Specifiche del Prodotto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX | |
| Imballo | FTBGA-256 |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX |
| Tipo | Descrizione | |
|---|---|---|
| Imballo | FTBGA-256 |
Descrizione
Low-power 3.3V 512-macrocell CPLD with 7.0 ns pin-to-pin logic delay, system frequency up to 135 MHz, 512 macrocells, 12,000 usable gate equivalents. 208-pin PQFP package (180 user I/Os) 256-ball FBGA package (212 user I/Os) 324-ball FBGA package (260 user I/Os) Optimized for 3.3V systems Ultra-low power operation Typical standby current of 18 μA at 25℃ 3.3V core supply with 5V-tolerant I/O pins Advanced 0.35-micron five-layer metal EEPROM process Fast Zero Power™ (FZP) CMOS design technology 3.3V PCI-compliant outputs (no internal clamp diodes on any input or I/O) The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V, 512-macrocell CPLD designed for power-sensitive applications requiring leading-edge programmable logic solutions. A total of 32 function blocks provide 12,000 usable gate equivalents. Pin-to-pin propagation delay as fast as 7.0 ns with a maximum system frequency of 135 MHz.
Caratteristiche
- Low-power 3.3V 512-macrocell CPLD
- Pin-to-pin logic delay of 7.0 ns
- System frequency up to 135 MHz
- 512 macrocells, 12,000 usable gates
- Optimized for 3.3V systems
- Ultra-low-power operation
- Typical standby current of 18 μA at 25℃
- 3.3V core supply with 5V-tolerant I/O pins
- Advanced 0.35-micron five-layer metal EEPROM process
- Fast Zero-Power™ (FZP) CMOS design technology
- 3.3V PCI-compliant outputs (no internal clamp diodes on any input or I/O)
- In-system programmable
- Input registers
- Predictable timing model
- Up to 23 clocks per function block
- Pin-locking on design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG) compliance
- Four global clocks
- Eight product-term control terms per function block
- Fast ISP programming time
- Port-enable pins for additional I/O
- Industrial supply voltage range: 2.7V to 3.6V
- Per-output programmable slew-rate control
- Security bit for unauthorized access protection
| Qtà | Pr. unit.(Solo per riferimento) | Importo totale |
|---|---|---|
| 1+ | $ 192.7649 | $ 192.76 |
| 200+ | $ 74.5975 | $ 14919.50 |
| 500+ | $ 71.9767 | $ 35988.35 |
| 1,000+ | $ 70.6814 | $ 70681.40 |
Package Standard90/Full Tray | ||
Specifiche del Prodotto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX | |
| Imballo | FTBGA-256 |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX |
| Tipo | Descrizione | |
|---|---|---|
| Imballo | FTBGA-256 |
Descrizione
Low-power 3.3V 512-macrocell CPLD with 7.0 ns pin-to-pin logic delay, system frequency up to 135 MHz, 512 macrocells, 12,000 usable gate equivalents. 208-pin PQFP package (180 user I/Os) 256-ball FBGA package (212 user I/Os) 324-ball FBGA package (260 user I/Os) Optimized for 3.3V systems Ultra-low power operation Typical standby current of 18 μA at 25℃ 3.3V core supply with 5V-tolerant I/O pins Advanced 0.35-micron five-layer metal EEPROM process Fast Zero Power™ (FZP) CMOS design technology 3.3V PCI-compliant outputs (no internal clamp diodes on any input or I/O) The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V, 512-macrocell CPLD designed for power-sensitive applications requiring leading-edge programmable logic solutions. A total of 32 function blocks provide 12,000 usable gate equivalents. Pin-to-pin propagation delay as fast as 7.0 ns with a maximum system frequency of 135 MHz.
Caratteristiche
- Low-power 3.3V 512-macrocell CPLD
- Pin-to-pin logic delay of 7.0 ns
- System frequency up to 135 MHz
- 512 macrocells, 12,000 usable gates
- Optimized for 3.3V systems
- Ultra-low-power operation
- Typical standby current of 18 μA at 25℃
- 3.3V core supply with 5V-tolerant I/O pins
- Advanced 0.35-micron five-layer metal EEPROM process
- Fast Zero-Power™ (FZP) CMOS design technology
- 3.3V PCI-compliant outputs (no internal clamp diodes on any input or I/O)
- In-system programmable
- Input registers
- Predictable timing model
- Up to 23 clocks per function block
- Pin-locking on design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG) compliance
- Four global clocks
- Eight product-term control terms per function block
- Fast ISP programming time
- Port-enable pins for additional I/O
- Industrial supply voltage range: 2.7V to 3.6V
- Per-output programmable slew-rate control
- Security bit for unauthorized access protection
Conformità & Codici di Esportazione
| Tipo | Dettagli |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Tipo | Dettagli |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Tipo | Dettagli |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |