NXP SPC5516EACMG48

The MPC5510 is a microcontroller product family available in multiple package options, including: MAPBGA-225 (15 mm × 15 mm), MAPBGA-208 (17 mm × 17 mm), LQFP-144 (20 mm × 20 mm), and LQFP-176 (24 mm × 24 mm).

• Single-issue 32-bit CPU core complex (e200z1), compliant with Power Architecture™ embedded category standard
• Instruction set enhancements supporting Variable Length Encoding (VLE) for code size reduction; optional mixed 16-bit and 32-bit instruction encoding enables significant code size reduction
• Up to 1.5-Mbyte on-chip flash with Flash Control Unit (FCU)
• Up to 80 Kbytes on-chip SRAM
• Memory Protection Unit (MPU) supporting up to sixteen region descriptors with 32-byte region granularity
• Interrupt Controller (INTC) capable of handling interrupt sources with selectable priority levels
• Integrated Frequency Modulated Phase-Locked Loop (FMPLL)
• Crossbar switch architecture supporting concurrent access to peripherals, flash, or RAM by multiple bus masters
• 16-channel enhanced Direct Memory Access controller (eDMA)
• Boot Assist Module (BAM) supporting internal flash programming via serial link (CAN or SCI)
• Timer with input/output channels providing a range of 16-bit input capture, output compare, and PWM functions (eMIOS200)
• Up to 40-channel 12-bit ADC
• Up to four Serial Peripheral Interface (DSPI) modules
• Media Local Bus (MLB) emulation logic, combinable with two DSPIs, e200z0, eDMA, and system RAM to create 3-pin or 5-pin 256Fs MLB protocol
• Up to eight enhanced Serial Communication Interface (eSCI) modules
• Up to six enhanced full-CAN (FlexCAN) modules with configurable buffers
• 1 I²C communication interface module
• Up to 144 configurable general-purpose pins supporting input/output operations at 3.0V to 5.5V supply levels
• Real-Time Counter (RTC_API) with clock source from external 32-kHz crystal oscillator, internal 32-kHz or 16-MHz oscillator; supports optional 1-second resolution wakeup with timeout greater than 1 hour, or 1-millisecond resolution with maximum timeout of 1 second
• Up to eight Periodic Interrupt Timers (PIT) with 32-bit counter resolution
• Nexus Development Interface (NDI), compliant with IEEE-ISTO 5001-2003 Class Two Plus standard
• IEEE-standard JTAG device/board-level test support (IEEE 1149.1)
• On-chip voltage regulator (VREG) regulating 5V input to 1.5V and 3.3V internal supply levels
• Optional e200z0, a second Power Architecture-based I/O processor with VLE instruction set support
• Optional FlexRAY controller
• Optional External Bus Interface (EBI) module