TI SN74AS280NS

These general-purpose 9-bit parity generators/checkers use Schottky-clamped TTL high-performance circuitry with odd/even outputs, suitable for both odd and even parity applications. Word length capacity can be easily expanded through cascading. The S280 can be used to improve the performance of most systems employing the DM74180 parity generator/checker. The S280 is not designed with an expand input; the corresponding function is implemented via pin 4, which connects all inputs, and pin 3, which has no internal connection. Input buffering is provided, with each input representing only one standard 74S load. Each output can drive a full fan-out of 10 standard 74S series loads at low logic level, and 20 standard 74S series loads at high logic level, making it convenient to connect unused inputs to used inputs.

• Odd or even parity generation for 9 data lines
• Cascadable for N-bit expansion
• Drop-in upgrade for existing MSI parity circuit systems
• Typical data-to-output propagation delay: 14 ns

• 25-line parity generator/checker
• 18-line or 27-line parity applications
• Parity generation for word lengths up to 81 bits