ADI ADSP-21478BSWZ-2A

The ADSP-2147x SHARC processors belong to the SIMD SHARC family of DSPs and employ a Super Harvard architecture. They are source-code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2116x DSPs, and the first-generation ADSP-2106x SHARC processors operating in SISD mode. These processors are 32/40-bit floating-point processors optimized for high-performance audio applications, featuring large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Application Interface (DAI).

• High-performance 32/40-bit floating-point processor optimized for high-performance audio processing
• Single Instruction, Multiple Data (SIMD) computational architecture
• On-chip memory: up to 5 Mb on-chip RAM, 4 Mb on-chip ROM
• Operating frequency up to 300 MHz
• Qualified for automotive applications
• Code-compatible with all other products in the SHARC family
• Audio-centric peripherals including digital application interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more
• Factory-programmed ROM versions include the latest Dolby and DTS audio decoders, available to IP license holders
• Two processing elements (PEx, PEy), each comprising an ALU, multiplier, shifter, and data register file
• Two data address generators (DAG1, DAG2)
• One program sequencer with instruction cache
• PM and DM buses supporting 2×64-bit data transfers per core processor cycle between memory and the core
• One interval timer with pin
• On-chip SRAM (up to 5 Mb)
• One JTAG test access port for emulation and boundary scan; JTAG provides software debug via user breakpoints with flexible exception handling support
• IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers
• Peripheral and external port buses for core connectivity
• External port with asynchronous memory interface (AMI) and SDRAM controller
• Four pulse width modulation (PWM) control units
• One memory-to-memory (MTM) unit for internal-to-internal memory transfers
• Digital application interface comprising 4 precision clock generators (PCG), 1 input data port for serial and parallel interconnect (IDP/PDAP), 1 S/PDIF receiver/transmitter, 4 asynchronous sample rate converters, 8 serial ports, 1 shift register, and 1 flexible signal routing unit (DAI SRU)
• Digital peripheral interface comprising 2 timers, 1 two-wire interface, 1 UART, 2 serial peripheral interfaces (SPI), 2 precision clock generators (PCG), 3 PWM units, and 1 flexible signal routing unit (DPI SRU)
• Delivers 1.8 GFLOPS utilizing SIMD compute hardware running at 300 MHz
• Many processor registers have shadow registers that can be activated during interrupt handling for fast context switching
• General-purpose registers available for common tasks; USTAT (4) registers enable easy bit manipulation (set, clear, toggle, test, XOR) on all peripheral control and status registers
• Data bus exchange register (PX) allows data transfer between the 64-bit PM data bus and 64-bit DM data bus, or between the 40-bit register file and the PM/DM data buses
• Enhanced Harvard architecture enabling simultaneous fetch of 4 operands (2 per data bus) and 1 instruction per cycle
• On-chip instruction cache supporting three-bus operation to fetch one instruction and four data values simultaneously
• Data address generators with zero-overhead hardware circular buffer support; two DAGs contain sufficient registers to create up to 32 circular buffers
• 48-bit instruction word supporting various parallel operations for compact programming
• Variable Instruction Set Architecture (VISA) support with new 16-bit and 32-bit instructions