NXP MCF54415CMJ250

Version 4 ColdFire Core with EMAC and MMU Up to 385 Dhrystone 2.1 MIPS @ 250 MHz 8 KB instruction cache and 8 KB data cache 64 KB internal SRAM dual-ported to processor local bus and other crossbar switch masters System boot from NOR, NAND, SPI flash, EEPROM, or FRAM Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters 64-channel DMA controller SDRAM controller supporting full-speed operation from a single x8 DDR2 component up to 250 MHz 32-bit FlexBus external memory interface for RAM, ROM, MRAM, and programmable logic USB 2.0 host controller USB 2.0 host/device/On-the-Go controller 8-bit single data rate ULPI port usable by the dedicated USB host module or the USB host/device/OTG module Dual 10/100 Ethernet MACs with hardware CRC checking/generation, IEEE 1588-2002 support, and optional Ethernet switch CPU direct-attached hardware accelerator for DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms Random number generator Enhanced Secure Digital host controller for SD, SDHC, SDIO, MMC, and MMCplus cards Two ISO7816 smart card interfaces Two FlexCAN modules Six I²C bus interfaces with DMA support in master mode Two synchronous serial interfaces Four 32-bit timers with DMA support Four programmable interrupt timers 8-channel, 16-bit motor control PWM timer Dual 12-bit ADCs with shared input channels and multiple conversion trigger sources Dual 12-bit DACs with DMA support 1-wire module with DMA support NAND flash controller Real-time clock with 32-kHz oscillator, 2 KB standby SRAM, and battery backup supply input Up to four DMA-supported serial peripheral interfaces (DSPI) Up to ten UARTs with single-wire mode support Up to five external IRQ interrupts and 2 external DMA request/acknowledge pairs Up to 16 processor local bus Rapid GPIO pins Up to 87 standard GPIO pins

• Version 4 ColdFire core with integrated EMAC and MMU
• Up to 250MHz operating frequency, 385 Dhrystone 2.1 MIPS performance
• 8KB instruction cache and 8KB data cache
• 64KB dual-port internal SRAM, accessible by processor local bus and other crossbar master devices
• System boot from NOR, NAND, SPI Flash, EEPROM, or FRAM
• Crossbar architecture supporting simultaneous multi-master access to peripherals or RAM
• 64-channel DMA controller
• SDRAM controller supporting single DDR2 component at full 250MHz operation
• 32-bit FlexBus external memory interface supporting RAM, ROM, MRAM, and programmable logic
• USB 2.0 host controller
• USB 2.0 host/device/On-the-Go controller
• 8-bit single data rate ULPI port, usable by dedicated USB host or USB host/device/OTG module
• Dual 10/100 Ethernet MAC with hardware CRC check and generation, IEEE 1588-2002 support, optional Ethernet switch capability
• CPU-direct hardware accelerator supporting DES, 3DES, AES, MD5, SHA-1, SHA-256
• Random number generator
• Enhanced secure digital host controller supporting SD, SDHC, SDIO, MMC, and MMCplus cards
• Two ISO7816 smart card interfaces
• Two FlexCAN modules
• Six I²C interfaces with DMA support in master mode
• Two synchronous serial interfaces
• Four DMA-capable 32-bit timers
• Four programmable interrupt timers
• 8-channel 16-bit motor control PWM timer
• Dual 12-bit ADC with shared input channels and multiple conversion trigger sources
• Dual DMA-capable 12-bit DAC
• DMA-capable 1-wire module
• NAND Flash controller
• Real-time clock with 32kHz oscillator, 2KB standby SRAM, and backup battery input
• Up to four DMA-capable DSPI interfaces
• Up to ten UARTs with single-wire mode support
• Up to five external IRQ interrupts and 2 external DMA request/acknowledge pairs
• Up to 16 processor local bus fast GPIO pins
• Up to 87 standard GPIO pins
• External filtering on analog VDD pins is recommended for improved noise isolation; a 10Ω resistor is required in the filter circuit, placed as close to the corresponding pin as possible; a 0Ω resistor may replace the 10Ω resistor for ADC power isolation to reduce IR drop and minimize additional gain error; MPU core digital power supply should be bypassed as much as routing allows, with bypass components placed as close to the pins as possible