TI TMS320DM642AGDK6

High- Performance Digital Media Processor 2- , 1.67- , 1.39- ns Instruction Cycle Time 500- , 600- , 720- MHz Clock Rate Eight 32- Bit Instructions/Cycle 4000, 4800, 5760 MIPS Fully Software- Compatible With C64xTM VelociTI.2TM Extensions to VelociTI TM Advanced Very- Long- Instruction- Word (VLIW) TMS320C64xTM DSP Core Eight Highly Independent Functional Units With VelociTI.2TM Extensions: Six ALUs (32- /40- Bit), Each Supports Single 32- Bit, Dual 16- Bit, or Quad 8- Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16- Bit Multiplies (32- Bit Results) per Clock Cycle or Eight 8 x 8- Bit Multiplies (16- Bit Results) per Clock Cycle Load- Store Architecture With Non- Aligned Support 64 32- Bit General- Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Byte- Addressable (8- /16- /32- /64- Bit Data) 8- Bit Overflow Protection Bit- Field Extract, Set, Clear Normalization, Saturation, Bit- Counting VelociTI.2TM Increased Orthogonality L1/L2 Memory Architecture 128K- Bit (16K- Byte) L1P Program Cache (Direct Mapped) 128K- Bit (16K- Byte) L1D Data Cache (2- Way Set- Associative) 2M- Bit (256K- Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian 64- Bit External Memory Interface (EMIF) Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)

• High-performance digital media processor; instruction cycle times of 2ns, 1.67ns, 1.39ns; clock frequencies of 500MHz, 600MHz, 720MHz; processes 8 32-bit instructions per clock cycle; compute performance of 4000MIPS, 4800MIPS, 5760MIPS; fully software-compatible with C64x™
• VelociTI™ advanced VLIW architecture with VelociTI.2™ extensions based on TMS320C64x™ DSP core; 8 highly independent functional units
• Six 32/40-bit ALUs, each supporting single 32-bit, dual 16-bit, or quad 8-bit operations per clock cycle
• Two multipliers, each supporting four 16×16-bit multiplications with 32-bit results, or eight 8×8-bit multiplications with 16-bit results per clock cycle
• Load/store architecture with unaligned memory access support; 64 32-bit general-purpose registers; instruction packing reduces code size; all instructions conditionally executable
• Byte-addressable instruction set supporting 8-bit, 16-bit, 32-bit, and 64-bit data; 8-bit overflow protection; bit-field extract, set, and clear operations; normalization, saturation, and bit-count support; VelociTI.2™ enhanced instruction orthogonality
• L1/L2 memory architecture: 128K-bit (16K-byte) direct-mapped L1P program cache; 128K-bit (16K-byte) 2-way set-associative L1D data cache; 2M-bit (256K-byte) unified mapped L2 RAM/cache; flexible RAM/cache partitioning
• Supports both little-endian and big-endian byte ordering
• Integrated 64-bit EMIF; glueless connection to asynchronous SRAM and EPROM, and synchronous SDRAM, SBSRAM, ZBT SRAM, and FIFO; total addressable external memory space of 1024M bytes
• Integrated EDMA controller with 64 independent channels
• Integrated 10/100Mb/s Ethernet MAC (EMAC); IEEE 802.3 compliant; MII interface; 8 independent transmit channels and 1 receive channel
• Integrated MDIO module
• Three configurable video ports; glueless connection to common video decoder and encoder devices; supports multiple resolutions and video standards
• Integrated VCXO interpolated control port (VIC) for audio/video synchronization
• Integrated HPI supporting 32-bit/16-bit data width
• Integrated 32-bit/66MHz, 3.3V PCI master/slave interface compliant with PCI 2.2
• Integrated McASP with 8 serial data pins; supports multiple I2S and similar bit-stream formats; integrated digital audio interface transmitter supporting S/PDIF, IEC60958-1, AES-3, and CP-430 formats
• Integrated I2C bus™
• Two integrated multi-channel buffered serial ports
• Three integrated 32-bit general-purpose timers
• 16 GPIO pins
• Integrated flexible PLL clock generator
• IEEE-1149.1 JTAG boundary scan compliant
• Two 548-pin BGA packages: 0.8mm ball pitch with GDK and ZDK suffixes; 1.0mm ball pitch with GNZ and ZNZ suffixes
• 0.13μm/6-layer copper metal CMOS process
• Two power supply configurations: 3.3V I/O with 1.2V core for -500 devices; 3.3V I/O with 1.4V core for A-500, A-600, -600, and -720 devices

• Video processing
• Imaging processing
• Digital multimedia processing