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TI SN74LVC2T45YZPRRoHS

Manufacturer
TI
MPN
SN74LVC2T45YZPR
LCSC Part #
C913828
Packaging
DSBGA-8
Customer #
Key Attributes
Dual-bit dual-supply bus transceiver with configurable voltage conversion
Datasheetpdf iconTI SN74LVC2T45YZPR
In-Stock: 1,394
1,394 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.6522$ 0.65
10+$ 0.5413$ 5.41
30+$ 0.494$ 14.82
100+$ 0.4337$ 43.37
500+$ 0.4076$ 203.80
1,000+$ 0.3913$ 391.30
Standard Packaging3000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Translators, Level Shifters
ManufacturerTI
PackagingDSBGA-8
output typeTri-State
Output Signal-
Input Signal-
Operating Temperature-40℃~+85℃
Data Rate420Mbps
Number of Elements1
Channel TypeBidirectional
FeaturesOutput enable high-impedance;Power-off protection
Voltage - Supply1.65V~5.5V;1.65V~5.5V
Number of Circuits2
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

This 2-bit in-phase bus transceiver uses two independent configurable power supply rails. Port A is designed to track VCCA. VCCA can accept any power supply voltage in the range from 1.65V to 5.5V. Port B is designed to track VCCB. VCCB can accept any power supply voltage value between 1.65V and 5.5V. This enables general low-voltage bidirectional conversion between 1.8V, 2.5V, 3.3V, and 5V voltage nodes. The SN74LVC2T45 is designed to achieve asynchronous communication between two data buses. The logic level of the direction control (DIR) input will activate the output of Port B or Port A. When the output of Port B is activated, the device sends data from Bus A to Bus B. When the output of Port A is activated, the device sends data from Bus B to Bus A. The input circuits on Port A and Port B are always active, and a logic high or low level must be applied to prevent excessive ICC and ICCZ. The SN74LVC2T45 is designed to be powered by VCCA for the DIR input circuit. This device fully meets the specification requirements for partial power-down applications using Ioff. The Ioff circuit disables the output to prevent destructive current from flowing back from the device when it is powered down. The VCC isolation feature ensures that as long as any VCC input is grounded (GND), both ports are in a high-impedance state.

Features

AI Translation
  • Fully configurable dual-rail design, supporting operation across the full supply voltage range of 1.65V to 5.5V on each port
  • VCC isolation feature – if either VCC input is tied to GND, both ports enter a high-impedance state
  • DIR input referenced to VCCA
  • Low power consumption, ICC maximum 4μA
  • NanoFree package
  • Output drive ±24mA at 3.3V
  • Ioff supports partial power-down mode operation
  • Maximum data rates:
    • 420Mbps (3.3V to 5V translation)
    • 210Mbps (translation to 3.3V)
    • 140Mbps (translation to 2.5V)
    • 75Mbps (translation to 1.8V)
  • Latch-up performance exceeds 100mA per JESD 78 Class II
  • ESD protection exceeds JESD 22 requirements:
    • 4000V Human Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged Device Model (C101)

Applications

AI Translation
  • Consumer Electronics
  • Industrial
  • Enterprise
  • Telecom