TOSHIBA 74VHC74FT(BJ)

The 74VHC74FT is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR(overline) are independent of the CK and are accomplished by setting the appropriate input low. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

• AEC-Q100 (Rev. H)
• Wide operating temperature range: T_opr = -40 to 125 ℃
• High speed: f_MAX = 170 MHz (typ.) at V_CC = 5.0 V
• Low power dissipation: I_CC = 2.0 μA (max) at T_a = 25 ℃
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Power-down protection is provided on all inputs.
• Balanced propagation delays: tp_LH ≈ tp_HL
• Wide operating voltage range: V_CC(opr) = 2.0 V to 5.5 V
• Pin and function compatible with the 74 series (74AC/HC/AHC etc.) 74 type.