ADI AD9363BBCZ-REEL

A high performance, highly integrated RF agile transceiver designed for use in 3G and 4G femtocell applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed - signal baseband section and integrated frequency synthesizers, simplifying design - in by providing a configurable digital interface to a processor. It operates in the 325 MHz to 3.8 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 20 MHz are supported. The two independent direct conversion receivers have state - of - the - art noise figure and linearity. Each Rx subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, eliminating the need for these functions in the digital baseband. It also has flexible manual gain modes that can be externally controlled. Two high dynamic range ADCs per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128 - tap finite impulse response (FIR) filters to produce a 12 - bit output signal at the appropriate sample rate. The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best - in - class Tx EVM of −34 dB, allowing significant system margin for the external power amplifier (PA) selection. The on - board Tx power monitor can be used as a power detector, enabling highly accurate Tx power measurements. The fully integrated phase - locked loops (PLLs) provide low power fractional N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by FDD systems, is integrated into the design. All voltage controlled oscillators (VCOs) and loop filter components are integrated. The core can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4 - wire serial port and four real - time I/O control pins. Comprehensive power - down modes are included to minimize power consumption during normal use. It is packaged in a 10 mm×10 mm, 144 - ball chip scale package ball grid array (CSP_BGA).

• Radio frequency (RF) z×2 transceiver with integrated 12 - bit DACs and ADCs
• Wide bandwidth: 325 MHz to 3.8 GHz
• Supports time division duplex (TDD) and frequency division duplex (FDD) operation
• Tunable channel bandwidth (BW): up to 20 MHz
• Receivers: 6 differential or 12 single - ended inputs
• Superior receiver sensitivity with a noise figure: 3 dB
• Receive (Rx) gain control: Real - time monitor and control signals for manual gain, Independent automatic gain control (AGC)
• Dual transmitters: 4 differential outputs
• Highly linear broadband transmitter
• Transmit (Tx) error vector magnitude (EVM): −34 dB
• Tx noise: ≤−157 dBm/Hz noise floor
• Tx monitor: 66 dB dynamic range with 1 dB accuracy
• Integrated fractional N synthesizers 2.4 Hz local oscillator (LO) step size
• CMOS/LVDS digital interface

• 3G enterprise femtocell base stations
• 4G femtocell base stations
• Wireless video transmission