NTE Electronics NTE74HC165
| Manufacturer | |
| MPN | NTE74HC165 |
| LCSC Part # | C7250443 |
| Packaging | DIP-16 |
| Customer # | |
| Key Attributes | 2V~6V 1 Parallel-to-Serial DIP-16 Shift Registers RoHS |
| Datasheet |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Shift Registers | |
| Manufacturer | NTE Electronics | |
| Packaging | DIP-16 | |
| Operating temperature | -55℃~+85℃ | |
| Voltage - Supply | 2V~6V | |
| Output Type | - | |
| Series | 74HC | |
| Number of Elements | 1 | |
| Features | Asynchronous parallel load function | |
| Function | Parallel-to-Serial |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Shift Registers | |
| Manufacturer | NTE Electronics | |
| Packaging | DIP-16 | |
| Operating temperature | -55℃~+85℃ | |
| Voltage - Supply | 2V~6V |
| Type | Description | |
|---|---|---|
| Output Type | - | |
| Series | 74HC | |
| Number of Elements | 1 | |
| Features | Asynchronous parallel load function | |
| Function | Parallel-to-Serial |
Introduction
The NTE74HC165 is an 8-bit parallel-in/serial-out shift register in a 16-pin DIP package, fabricated using advanced silicon-gate CMOS technology. It offers the high noise immunity and low power consumption characteristic of standard CMOS ICs, while being capable of driving 10 LS-TTL loads. This 8-bit serial shift register shifts data from QA to QH on each clock pulse. Parallel inputs at each stage are enabled by a low level on the SHIFT/LOAD input. A gated clock input and complementary output from the eighth bit are also provided. Clock operation is implemented through a 2-input NOR gate, allowing one input to serve as a clock inhibit function. Holding either clock input HIGH inhibits clock operation; holding either clock input LOW with the SHIFT/LOAD input HIGH enables the other clock input. Data transfer occurs on the rising edge of the clock. Parallel loading is inhibited as long as the SHIFT/LOAD input remains HIGH. When this input is LOW, data at the parallel inputs is loaded directly into the register regardless of the clock state. The 74HC logic family is functionally and pin-compatible with the standard 74LS logic family. All inputs are protected against ESD damage by diodes connected to VCC and GND.
Features
- Typical propagation delay: clock to Q 20ns
- Low quiescent current: 80μA max
- Low input current: 1μA max
- Wide supply voltage range: 2V to 6V
- Fan-out: drives 10 LS-TTL loads
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 2.3292 | $ 2.33 |
| 200+ | $ 0.9305 | $ 186.10 |
| 500+ | $ 0.8987 | $ 449.35 |
| 1,000+ | $ 0.8835 | $ 883.50 |
Standard Packaging1/Full Bag | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Shift Registers | |
| Manufacturer | NTE Electronics | |
| Packaging | DIP-16 | |
| Operating temperature | -55℃~+85℃ | |
| Voltage - Supply | 2V~6V | |
| Output Type | - | |
| Series | 74HC | |
| Number of Elements | 1 | |
| Features | Asynchronous parallel load function | |
| Function | Parallel-to-Serial |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Shift Registers | |
| Manufacturer | NTE Electronics | |
| Packaging | DIP-16 | |
| Operating temperature | -55℃~+85℃ | |
| Voltage - Supply | 2V~6V |
| Type | Description | |
|---|---|---|
| Output Type | - | |
| Series | 74HC | |
| Number of Elements | 1 | |
| Features | Asynchronous parallel load function | |
| Function | Parallel-to-Serial |
Introduction
The NTE74HC165 is an 8-bit parallel-in/serial-out shift register in a 16-pin DIP package, fabricated using advanced silicon-gate CMOS technology. It offers the high noise immunity and low power consumption characteristic of standard CMOS ICs, while being capable of driving 10 LS-TTL loads. This 8-bit serial shift register shifts data from QA to QH on each clock pulse. Parallel inputs at each stage are enabled by a low level on the SHIFT/LOAD input. A gated clock input and complementary output from the eighth bit are also provided. Clock operation is implemented through a 2-input NOR gate, allowing one input to serve as a clock inhibit function. Holding either clock input HIGH inhibits clock operation; holding either clock input LOW with the SHIFT/LOAD input HIGH enables the other clock input. Data transfer occurs on the rising edge of the clock. Parallel loading is inhibited as long as the SHIFT/LOAD input remains HIGH. When this input is LOW, data at the parallel inputs is loaded directly into the register regardless of the clock state. The 74HC logic family is functionally and pin-compatible with the standard 74LS logic family. All inputs are protected against ESD damage by diodes connected to VCC and GND.
Features
- Typical propagation delay: clock to Q 20ns
- Low quiescent current: 80μA max
- Low input current: 1μA max
- Wide supply voltage range: 2V to 6V
- Fan-out: drives 10 LS-TTL loads
C7250443 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

