NTE Electronics NTE74HC299

The NTE74HC299 is an 8-bit shift/storage register in a 20-pin DIP package with three-state bus interface capability. The register has four synchronous operating modes controlled by two select inputs, as shown in the Mode Select (S0, S1) table. Mode select, serial data (DS0, DS7), and parallel data (I/O0–I/O7) respond only to low-to-high transitions of the clock (CP) pulse. S0, S1, and data inputs must be stable for one setup time prior to the positive clock transition. Master Reset (MR) is an asynchronous active-low input. When MR is low, the register is cleared regardless of all other input states. Identical units can be cascaded to expand the register by connecting the serial output (Q0) to the serial data input (DS7) of the preceding register, and the serial output (Q7) to the serial data input (DS0) of the following register. An (n × 8)-bit recirculating loop can be achieved by connecting Q7 of the last stage to DS0 of the first stage. The three-state I/O port has three operating modes: 1. When both output enables (OE1 and OE2) are low and S0, S1, or both are low, the data in the register is presented at the eight outputs. 2. When both S0 and S1 are high, the I/O terminals are in the high-impedance state; however, as input ports, parallel data can be loaded into the eight registers within one clock transition regardless of the states of OE1 and OE2. 3. Either output enable input being high forces the I/O terminals to the off state. Note that each I/O terminal is a three-state output and a CMOS buffered input.

• Wide supply voltage range: 2V to 6V
• High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• Buffered inputs
• Four operating modes: shift left, shift right, load, and store
• Cascadable for N-bit word length
• I/O0–I/O7 bus drive capability and three-state for bus-oriented applications
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = +25°C
• Fan-out (over temperature range): standard outputs... 10 LS-TTL loads; bus driver outputs... 15 LS-TTL loads
• Balanced propagation delay and transition times
• Significantly reduced power consumption compared to LS-TTL logic ICs