NTE Electronics NTE74LS192
| Manufacturer | |
| MPN | NTE74LS192 |
| LCSC Part # | C6622705 |
| Packaging | PDIP-16 |
| Customer # | |
| Key Attributes | Rising Edge 1 32MHz PDIP-16 Counters, Dividers RoHS |
| Datasheet |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | NTE Electronics | |
| Packaging | PDIP-16 | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V~5.25V | |
| Direction | Up Counter;Down Counter | |
| Trigger Type | Rising Edge | |
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | - | |
| Count Rate | 32MHz | |
| Features | Programmable divide ratio;Synchronous counting;Cascade counter;Reset function |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | NTE Electronics | |
| Packaging | PDIP-16 | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V~5.25V | |
| Direction | Up Counter;Down Counter | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | - | |
| Count Rate | 32MHz | |
| Features | Programmable divide ratio;Synchronous counting;Cascade counter;Reset function |
Introduction
The NTE74LS192 is a synchronous BCD up/down counter in a 16-pin plastic DIP package, equivalent to 55 gate equivalents. Synchronous operation is achieved by clocking all flip-flops simultaneously, causing the outputs to change at the same time under direction of the control logic. This mode of operation eliminates the output counting spikes typically associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high transition of either count (clock) input. The count direction is determined by which count input is pulsed, while the other count input is held high. The counter is fully programmable — that is, each output can be preset to either level by entering the desired data at the data inputs when the load input is low. The outputs will conform to the data inputs independently of the count pulses. This feature allows simple modification of count length via the preset inputs, enabling use of the counter as a divide-by-N circuit. A clear input is provided which, when taken high, forces all outputs low. The clear function operates independently of the count and load inputs. The clear, count, and load inputs are all buffered to reduce drive requirements, thereby minimizing the number of clock drivers and similar components required for long words. The device is designed to cascade without external circuitry. Both borrow and carry outputs are available for cascading the up- and down-counting functions. When an overflow condition exists, the borrow output generates a pulse with a width equal to the up-count input. Counter cascading is then easily accomplished by feeding the borrow and carry outputs to the down-count and up-count inputs of the subsequent counter, respectively.
Features
- Internal cascade circuit provided
- Synchronous operation
- Individual preset per flip-flop
- Fully independent clear input
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 16.1478 | $ 16.15 |
| 200+ | $ 6.444 | $ 1288.80 |
| 500+ | $ 6.2288 | $ 3114.40 |
| 1,000+ | $ 6.1212 | $ 6121.20 |
Standard Packaging10/Full Bag | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | NTE Electronics | |
| Packaging | PDIP-16 | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V~5.25V | |
| Direction | Up Counter;Down Counter | |
| Trigger Type | Rising Edge | |
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | - | |
| Count Rate | 32MHz | |
| Features | Programmable divide ratio;Synchronous counting;Cascade counter;Reset function |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | NTE Electronics | |
| Packaging | PDIP-16 | |
| Logic Family | 74LS | |
| Voltage - Supply | 4.75V~5.25V | |
| Direction | Up Counter;Down Counter | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Timing | Synchronous | |
| Operating Temperature | 0℃~+70℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | - | |
| Count Rate | 32MHz | |
| Features | Programmable divide ratio;Synchronous counting;Cascade counter;Reset function |
Introduction
The NTE74LS192 is a synchronous BCD up/down counter in a 16-pin plastic DIP package, equivalent to 55 gate equivalents. Synchronous operation is achieved by clocking all flip-flops simultaneously, causing the outputs to change at the same time under direction of the control logic. This mode of operation eliminates the output counting spikes typically associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high transition of either count (clock) input. The count direction is determined by which count input is pulsed, while the other count input is held high. The counter is fully programmable — that is, each output can be preset to either level by entering the desired data at the data inputs when the load input is low. The outputs will conform to the data inputs independently of the count pulses. This feature allows simple modification of count length via the preset inputs, enabling use of the counter as a divide-by-N circuit. A clear input is provided which, when taken high, forces all outputs low. The clear function operates independently of the count and load inputs. The clear, count, and load inputs are all buffered to reduce drive requirements, thereby minimizing the number of clock drivers and similar components required for long words. The device is designed to cascade without external circuitry. Both borrow and carry outputs are available for cascading the up- and down-counting functions. When an overflow condition exists, the borrow output generates a pulse with a width equal to the up-count input. Counter cascading is then easily accomplished by feeding the borrow and carry outputs to the down-count and up-count inputs of the subsequent counter, respectively.
Features
- Internal cascade circuit provided
- Synchronous operation
- Individual preset per flip-flop
- Fully independent clear input
C6622705 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

