LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
NTE Electronics NTE74LS192 product image
Images for reference only

NTE Electronics NTE74LS192RoHS

Manufacturer
MPN
NTE74LS192
LCSC Part #
C6622705
Packaging
PDIP-16
Customer #
Key Attributes
Rising Edge 1 32MHz PDIP-16 Counters, Dividers RoHS
Datasheetpdf iconNTE Electronics NTE74LS192
Out of Stock
Notify Me
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit Price(Reference Only)Total Amount
1+$ 16.1478$ 16.15
200+$ 6.444$ 1288.80
500+$ 6.2288$ 3114.40
1,000+$ 6.1212$ 6121.20
Standard Packaging10/Full Bag
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Counters, Dividers
ManufacturerNTE Electronics
PackagingPDIP-16
Logic Family74LS
Voltage - Supply4.75V~5.25V
DirectionUp Counter;Down Counter
Trigger TypeRising Edge
TimingSynchronous
Operating Temperature0℃~+70℃
ResetAsynchronous
Number of Elements1
Propagation Delay-
Count Rate32MHz
FeaturesProgrammable divide ratio;Synchronous counting;Cascade counter;Reset function

Introduction

AI Translation

The NTE74LS192 is a synchronous BCD up/down counter in a 16-pin plastic DIP package, equivalent to 55 gate equivalents. Synchronous operation is achieved by clocking all flip-flops simultaneously, causing the outputs to change at the same time under direction of the control logic. This mode of operation eliminates the output counting spikes typically associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high transition of either count (clock) input. The count direction is determined by which count input is pulsed, while the other count input is held high. The counter is fully programmable — that is, each output can be preset to either level by entering the desired data at the data inputs when the load input is low. The outputs will conform to the data inputs independently of the count pulses. This feature allows simple modification of count length via the preset inputs, enabling use of the counter as a divide-by-N circuit. A clear input is provided which, when taken high, forces all outputs low. The clear function operates independently of the count and load inputs. The clear, count, and load inputs are all buffered to reduce drive requirements, thereby minimizing the number of clock drivers and similar components required for long words. The device is designed to cascade without external circuitry. Both borrow and carry outputs are available for cascading the up- and down-counting functions. When an overflow condition exists, the borrow output generates a pulse with a width equal to the up-count input. Counter cascading is then easily accomplished by feeding the borrow and carry outputs to the down-count and up-count inputs of the subsequent counter, respectively.

Features

AI Translation
  • Internal cascade circuit provided
  • Synchronous operation
  • Individual preset per flip-flop
  • Fully independent clear input