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MICROCHIP PIC24FJ32GA102-I/SS product image
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MICROCHIP PIC24FJ32GA102-I/SSRoHS

Manufacturer
MPN
PIC24FJ32GA102-I/SS
LCSC Part #
C641956
Packaging
SSOP-28-208mil
Customer #
Key Attributes
Pin, 16-Bit General Purpose Flash Microcontrollers with nano Watt XLP Technology
Datasheetpdf iconMICROCHIP PIC24FJ32GA102-I/SS
In-Stock: 23
23 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
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QtyUnit PriceTotal Amount
1+$ 6.6545$ 2.1960$ 2.20
10+$ 6.3632$ 2.0999$ 21.00
30+$ 6.1849$ 2.0411$ 61.23
100+$ 6.0362$ 1.9920$ 199.20
Standard Packaging47/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerMICROCHIP
PackagingSSOP-28-208mil
ADC (Bit)10bit
Operating Temperature-40℃~+85℃
Program Memory TypeFLASH
Voltage - Supply2V~3.6V
EEPROM-
Program Storage Size32KB
CPU CorePIC
Core Size16 Bit
CPU Maximum Speed32MHz
Oscillator TypeBuilt-in
Number of I/O21

Introduction

AI Translation

28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology

Features

AI Translation
  • Selectable Power Management modes with nanoWatt XLP Technology for Extremely Low Power
  • Deep Sleep mode allows near total power-down (20 nA typical and 500 nA with RTCC or WDT), along with the ability to wake-up on external triggers, or self-wake on programmable WDT or RTCC alarm
  • Extreme low-power DSBOR for Deep Sleep, LPBOR for all other modes
  • Sleep mode shuts down peripherals and core for substantial power reduction, fast wake-up
  • Idle mode shuts down the CPU and peripherals for significant power reduction, down to 4.5 μA typical
  • Doze mode enables CPU clock to run slower than peripherals
  • Alternate Clock modes allow on-the-fly switching to a lower clock speed for selective power reduction during Run mode, down to 15 μA typical
  • Modified Harvard Architecture
  • Up to 16 MIPS Operation @ 32 MHz
  • 8 MHz Internal Oscillator with: - 4x PLL option Multiple divide options
  • 17-Bit x 17-Bit Single-Cycle Hardware Fractional integer Multiplier
  • 32-Bit by 16-Bit Hardware Divider
  • 16 x 16-Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture: 76 base instructions - Flexible addressing modes
  • Linear Program Memory Addressing, up to 12 Mbytes
  • Linear Data Memory Addressing, up to 64 Kbytes
  • Two Address Generation Units for Separate Read and Write Addressing of Data Memory
  • Operating Voltage Range of 2.0V to 3.6V
  • Self-Reprogrammable under Software Control
  • 5.5V Tolerant Input (digital pins only)
  • High-Current Sink/Source (18 mA/18 mA) on All I/O pins
  • Flash Program Memory: 10,000 erase/write cyc