LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
NTE Electronics NTE74193 product image
Images for reference only

NTE Electronics NTE74193

Manufacturer
MPN
NTE74193
LCSC Part #
C6345915
Packaging
PDIP-16
Customer #
Key Attributes
Rising Edge 1 32MHz PDIP-16 Counters, Dividers
Datasheetpdf iconNTE Electronics NTE74193
Out of Stock
Notify Me
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit Price(Reference Only)Total Amount
1+$ 5.4801$ 5.48
200+$ 2.1869$ 437.38
500+$ 2.1142$ 1057.10
1,000+$ 2.0778$ 2077.80
Standard Packaging1/Full Bag
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Counters, Dividers
ManufacturerNTE Electronics
PackagingPDIP-16
Logic Family-
Voltage - Supply4.75V~5.25V
DirectionUp Counter;Down Counter
Trigger TypeRising Edge
TimingSynchronous
Operating Temperature0℃~+70℃
ResetAsynchronous
Number of Elements1
Propagation Delay25ns@5V,15pF;31ns@5V,15pF
Count Rate32MHz
FeaturesProgrammable divide ratio;Synchronous counting;Cascade counter;Reset function

Introduction

AI Translation

The NTE74193 is a synchronous 4-bit binary up/down counter in a 16-pin plastic DIP package with an equivalent gate count of 55. Synchronous operation is achieved by clocking all flip-flops simultaneously, causing the outputs to change at the same time under the direction of the control logic. This mode of operation eliminates the output counting spikes typically associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by the low-to-high transition of either count (clock) input. The counting direction is determined by which count input is pulsed, while the other count input is held high. The counter is fully programmable — when the load input is low, each output can be preset to either level by entering the desired data at the data inputs. The outputs will conform to the data inputs independently of the count pulses. This feature allows simple modification of count length by using preset inputs, enabling the counter to function as a divide-by-N counter. A clear input is provided which, when driven high, forces all outputs low. The clear function operates independently of the count and load inputs. The clear, count, and load inputs are all buffered to reduce drive requirements, minimizing the number of clock drivers and similar components needed for long word lengths. The device is designed to cascade without external circuitry. Both borrow and carry outputs are available for cascading up-counting and down-counting operations. When an overflow condition exists, the borrow output generates a pulse with a width equal to the up-count input. Counter cascading is then easily accomplished by feeding the borrow and carry outputs into the down-count and up-count inputs of the subsequent counter, respectively.

Features

AI Translation
  • Internal cascade circuit provided
  • Synchronous operation
  • Individual preset per flip-flop
  • Fully independent clear input