SKYWORKS 565BAA2350M00BCG

The Si565 Super-Family voltage-controlled crystal oscillator uses Skyworks Solutions' advanced 4th-generation DSPLL technology to deliver ultra-low jitter, low phase noise clocks at any output frequency. The device is factory-programmed to any frequency from 0.2 to 3000 MHz with resolution of less than 1 ppb, and maintains ultra-low jitter for both integer and fractional frequencies across its operating range. On-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low-jitter clocks in noisy systems using switching power supplies. The Si565 is available in industry-standard packages, greatly simplifying the supply chain and enabling Silicon Labs to deliver custom-frequency samples within 1–2 weeks of order receipt. Unlike traditional XOs, which require a different crystal for each output frequency, the Si565 uses a single crystal and DSPLL IC-based approach to provide the required output frequency. The Si565 can be factory-configured for a wide range of user specifications, including frequency, output format, and OE pin position/polarity. Specific configurations are factory-programmed at the time of shipment, eliminating the long lead times associated with custom oscillators. Package sizes are available in 5×7 mm, 3.2×5 mm, and 2.5×3.2 mm.

• Any frequency from 200 kHz to 3000 MHz
• Ultra-low jitter: 100 fs RMS typical (12 kHz - 20 MHz)
• Excellent PSRR and power supply noise immunity: -80 dBc typical
• Single device operates from 3.3V, 2.5V, and 1.8V VDD supplies
• LVPECL, LVDS, CML, HCSL, CMOS, and dual CMOS output options
• Available in 2.5×3.2, 3.2×5, and 5×7 mm packages
• Samples available in 1-2 weeks

• 100G/200G/400G optical transport network, coherent optical
• 10G/25G/40G/100G Ethernet
• 56G/112G PAM4 clocking
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage devices, NICs, search acceleration
• Test and measurement
• FPGA/ASIC clocking