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Nexperia 74LVC32APW,118 product image
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Nexperia 74LVC32APW,118RoHS

Manufacturer
MPN
74LVC32APW,118
LCSC Part #
C6087
Packaging
TSSOP-14
Customer #
Key Attributes
Quad 2-input OR gate
Datasheetpdf iconNexperia 74LVC32APW,118
In-Stock: 19,945
19,945 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.1295$ 0.65
50+$ 0.1015$ 5.08
150+$ 0.0874$ 13.11
500+$ 0.0769$ 38.45
2,500+$ 0.0685$ 171.25
5,000+$ 0.0642$ 321.00
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerNexperia
PackagingTSSOP-14
Logic Family74LVC Series
Voltage - Supply1.2V~3.6V
Output Logic Level - Low200mV;450mV;600mV;400mV;800mV
Propagation Delay5ns@3.3V,50pF
FeaturesOvervoltage-tolerant input
Input Logic Level - Low120mV~800mV
Input Logic Level - High1.08V~2V
Operating Temperature-40℃~+125℃
Output Logic Level - High1.2V;1.8V;2.2V;2.4V
Quiescent Current(Iq)40uA
Current - Output High(IOH)24mA
Number of Channels4;2
Current - Output Low(IOL)24mA

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

The 74LVC32A is a quad 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

Features

AI Translation
  • Wide supply voltage range from 1.2 V to 3.6 V
  • Overvoltage tolerant inputs to 5.5 V
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

AI Translation
  • Level translation in mixed 3.3V and 5V environments