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Intel/Altera EP3C25E144I7N product image
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Intel/Altera EP3C25E144I7NRoHS

Manufacturer
Intel/Altera
MPN
EP3C25E144I7N
LCSC Part #
C568974
Packaging
LQFP-144-EP(20x20)
Customer #
Key Attributes
24624 1539 LQFP-144-EP(20x20) FPGAs (Field Programmable Gate Array) RoHS
Datasheetpdf iconIntel/Altera EP3C25E144I7N
In-Stock: 2
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QtyUnit PriceTotal Amount
1+$ 117.8197$ 117.82
3+$ 109.1339$ 327.40
30+$ 103.7254$ 3111.76
Standard Packaging60/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array)
ManufacturerIntel/Altera
PackagingLQFP-144-EP(20x20)
Embedded Block RAM608256bit
Voltage - Supply(VCCIO)-
Number of Logic Elements/Blocks24624
Logic Array Blocks1539
Operating Temperature-40℃~+100℃
Type-
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Features

AI Translation
  • Lowest Power FPGAs
  • Design Security Feature
  • Increased System Integration
  • LE Features
  • Control Signals
  • Parity Bit Support
  • Byte Enable Support
  • Packed Mode Support
  • Address Clock Enable Support
  • Mixed-Width Support
  • Asynchronous Clear
  • Memory Modes
  • Clocking Modes
  • Embedded Multiplier Block Overview
  • Architecture
  • Operational Modes
  • Clock Networks
  • GCLK Network
  • Clock Control Block
  • GCLK Network Clock Source Generation
  • GCLK Network Power Down
  • clkena Signals
  • Cyclone III Device Family PLL Hardware Overview
  • External Clock Outputs
  • Clock Feedback Modes
  • Hardware Features
  • Clock Multiplication and Division
  • Post-Scale Counter Cascading
  • Programmable Duty Cycle
  • PLL Control Signals
  • Clock Switchover
  • Automatic Clock Switchover
  • Manual Override
  • Manual Clock Switchover
  • Guidelines
  • Programmable Bandwidth
  • Phase Shift Implementation
  • PLL Cascading
  • PLL Reconfiguration
  • PLL Reconfiguration Hardware Implementation
  • Post-Scale Counters (C0 to C4)
  • Scan Chain Description
  • Charge Pump and Loop Filter
  • Bypassing PLL Counter
  • Dynamic Phase Shifting
  • Spread-Spectrum Clocking
  • Cyclone III Device Family I/O Elements
  • I/O Element Features
  • Programmable Current Strength
  • Slew Rate Control
  • Open-Drain Output
  • Bus Hold
  • Programmable Pull-Up Resistor
  • Programmable Delay
  • PCI-Clamp Diode
  • LVDS Transmitter Programmable Pre-Emphasis
  • OCT Support
  • On-Chip Series Termination with Calibration
  • On-Chip Series Termination Without Calibration
  • I/O Standards
  • Termination Scheme for I/O Standards
  • Voltage-Referenced I/O Standard Termination
  • Differential I/O Standard Termination
  • I/O Banks
  • High-Speed Differential Interfaces
  • External Memory Interfacing
  • Pad Placement and DC Guidelines
  • Pad Placement
  • DC Guidelines
  • High-Speed I/O Interface
  • High-Speed I/O Standards Support
  • LVDS I/O Standard Support in the Cyclone III Device Family
  • Designing with LVDS
  • BLVDS I/O Standard Support in the Cyclone III Device Family
  • Designing with BLVDS
  • RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family
  • Designing with RSDS, Mini-LVDS, and PPDS
  • LVPECL I/O Support in the Cyclone III Device Family
  • Differential SSTL I/O Standard Support in the Cyclone III Device Family
  • Differential HSTL I/O Standard Support in the Cyclone III Device Family
  • True Output Buffer Feature
  • Programmable Pre-Emphasis
  • High-Speed I/O Timing
  • Design Guidelines
  • Differential Pad Placement Guidelines
  • Board Design Considerations
  • Software Overview
  • Cyclone III Device Family Memory Interfaces Pin Support
  • Data and Data Clock/Strobe Pins
  • Optional Parity, DM, and Error Correction Coding Pins
  • Address and Control/Command Pins
  • Memory Clock Pins
  • Cyclone III Device Family Memory Interfaces Features
  • DDR Input Registers
  • DDR Output Registers
  • OCT
  • PLL