onsemi NCH-RSL10-101WC51-ABG

RSL10 is an ultra−low−power, highly flexible multi−protocol 2.4 GHz radio specifically designed for use in high−performance wearable and medical applications. With its Arm Cortex -M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low energy technology and 2.4 GHz proprietary protocol stacks, without sacrificing power consumption.

• Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −94 dBm
• Data Rate: 62.5 to 2000 kbps
• Transmitting Power: -17 to +6 dBm
• Peak Rx Current = 5.6 mA (1.25 V VBAT)
• Peak Rx Current = 3.0 mA (3 V VBAT)
• Peak Tx Current (0 dBm)=8.9 mA (1.25 V VBAT)
• Peak Tx Current (0 dBm)=4.6 mA (3 V VBAT)
• Bluetooth 5 Certified
• Support for Bluetooth 5 features: LE 2−Mbit PHY (High Speed), as well as backwards compatibility and support for earlier Bluetooth Low Energy specifications
• Arm Cortex−M3 Processor Clocked at up to 48 MHz
• LPDSP32 for Audio Codec
• Supply Voltage Range: 1.1 − 3.3 V
• Current Consumption (1.25 V VBAT):
  • Deep Sleep, IO Wake−up: 50 nA
  • Deep Sleep, 8 kB RAM Retention: 300 nA
  • Audio Streaming at 7 kHz Audio BW: 1.8 mA RX, 1.8 mA TX
• Current Consumption (3 V VBAT):
  • Deep Sleep, IO Wake−up: 25 nA
  • Deep Sleep, 8 kB RAM Retention: 100 nA
  • Audio Streaming at 7 kHz Audio BW: 0.9 mA RX, 0.9 mA TX
• 384 kB of Flash Memory
• Highly−integrated System−on−Chip (SoC)
• Supports FOTA (Firmware Over−The−Air) Updates
• Arm Cortex−M3 Processor: A 32−bit core for real−time applications, specifically developed to enable high−performance low−cost platforms for a broad range of low−power applications.
• LPDSP32: A 32−bit Dual Harvard DSP core that efficiently supports audio codecs required for wireless audio communication. Various codecs are available to customers through libraries that are included in RSL10’s development tools.
• Radio Frequency Front−End: Based on a 2.4 GHz RF transceiver, the RFFE implements the physical layer of the Bluetooth low energy technology standard and other proprietary or custom protocols.
• Protocol Baseband Hardware: Bluetooth 5 certified and includes support for a 2 Mbps RF link and custom protocol options. The RSL10 baseband stack is supplemented by support structures that enable implementation of ON Semiconductor and customer designed custom protocols.
• Highly−Integrated SoC: The dual−core architecture is complemented by high−efficiency power management units, oscillators, flash and RAM memories, a DMA controller, along with a full complement of peripherals and interfaces.
• Deep Sleep Mode: RSL10 can be put into a Deep Sleep Mode when no operations are required. Various Deep Sleep Mode configurations are available, including:
  • “IO wake−up” configuration. The power consumption in deep sleep mode is 50 nA (1.25 V VBAT).
  • Embedded 32 kHz oscillator running with interrupts from timer or external pin. The total current drain is 90 nA (1.25 V VBAT).
  • As above with 8 kB RAM data retention. The total current drain is 300 nA (1.25 V VBAT).
  • The DC−DC converter can be used in buck mode or LDO mode during Sleep Mode, depending on VBAT voltage.
• Standby Mode: Can be used to reduce the average power consumption for off−duty cycle operation, ranging typically from a few ms to a few hundreds of ms. The typical chip power consumption is 30 μA in Standby Mode.
• Multi−Protocol Support: Using the flexibility provided by LPDSP32, the Arm Cortex−M3 processor, and the RF front−end; proprietary protocols and other custom protocols are supported.
• Flexible Supply Voltage: RSL10 integrates high− efficiency power regulators and has a VBAT range of 1.1 to 3.3 V.
• Highly Configurable Interfaces: I²C, UART, two SPI interfaces, PCM interface, multiple GPIOs. It also supports a digital microphone interface (DMIC) and an output driver (OD).
• The Asynchronous Sample Rate Converter (ASRC) Block and Audio Sink Clock Blocks: Provides a means of synchronizing the audio sample rate between an audio source and an audio sink. The audio sink clock also provides a high accuracy mechanism to measure an input clock used for the RTC or protocol timing.
• Flexible Clocking Scheme: RSL10 must be clocked from the XTAL/PLL of the radio front−end at 48 MHz when transmitting or receiving RF traffic. When RSL10 is not transmitting/receiving RF traffic, it can run off the 48 MHz XTAL, the internal RC oscillators, the 32 kHz oscillator, or an external clock. A low frequency RTC clock at 32 kHz can also be used in Deep Sleep Mode. It can be sourced from either the internal XTAL, the RC oscillator, or a digital input pad.
• Diverse Memory Architecture: 76 kB of SRAM program memory (4 kB of which is PROM containing the chip boot−up program, and is thus unavailable to the user) and 88 kB of SRAM data memory are available. A total of 384 kB of flash is available to store the Bluetooth stack and other applications. The Arm Cortex−M3 processor can execute from SRAM and/or flash.
• Security: AES128 encryption hardware block for custom secure algorithms and code protection with authenticated debug port access (JTAG ‘lock’)