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Nexperia 74LVC2G02DC-Q100H product image
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Nexperia 74LVC2G02DC-Q100HRoHS

Manufacturer
Nexperia
MPN
74LVC2G02DC-Q100H
LCSC Part #
C548536
Packaging
VSSOP-8-0.5mm
Customer #
Key Attributes
Dual 2-input NOR gate
Datasheetpdf iconNexperia 74LVC2G02DC-Q100H
In-Stock: 3,022
3,022 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.5663$ 0.57
10+$ 0.4593$ 4.59
30+$ 0.4057$ 12.17
100+$ 0.3522$ 35.22
500+$ 0.3213$ 160.65
1,000+$ 0.3035$ 303.50
Standard Packaging3000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerNexperia
PackagingVSSOP-8-0.5mm
Input Logic Level - High-
Input Logic Level - Low-
FeaturesLocal shutdown mode;Overvoltage-tolerant input
Operating Temperature-40℃~+125℃
Logic Family74LVC
Output Logic Level - High-
Quiescent Current(Iq)4uA
Voltage - Supply1.65V~5.5V
Current - Output High(IOH)24mA
Number of Channels2;2
Output Logic Level - Low-
Propagation Delay4.3ns@4.5V~5.5V,50pF
Current - Output Low(IOL)24mA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The 74LVC2G02-Q100 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

AI Translation
  • Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant outputs for interfacing with 5 V logic
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Applications

AI Translation
  • Automotive applications