TECH PUBLIC 74LVC125APW-TP

This is a quad buffer/line driver with 3-state outputs controlled by an output enable input (nOE). When nOE is high, the outputs are in a high-impedance off state. The inputs can be driven by 2.7 V or 3.3 V devices. This feature allows these devices to be used as translators in mixed 2.7 V and 3.3 V environments. Schmitt-trigger action on all inputs enables the circuit to tolerate slower input rise and fall times. This device is fully specified for partial-power-down applications using IOFF.

• Wide supply voltage range: 1.65 V to 3.6 V
• CMOS low power consumption
• Overvoltage-tolerant inputs up to 5.5 V
• Latch-up performance exceeds 250 mA
• Direct TTL-level interface capability
• ESD protection: HBM ANSI/ESDA/JEDEC JS-003 Class A exceeds 6000 V, CDM ANSI/ESDA/JEDEC JS-002 C3 exceeds 2000 V
• I_OFF circuitry enables partial power-down mode operation
• JEDEC standards compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V)
• Package: TSSOP-14