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XINLUDA XL9535QF24 product image
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XINLUDA XL9535QF24RoHS

Manufacturer
XINLUDAAsian Brands
MPN
XL9535QF24
LCSC Part #
C5444301
Packaging
QFN-24(4x4)
Customer #
Key Attributes
16-bit I²C-bus and SMBus I/O port Expander With Interrupt Output and Configuration Registers
Datasheetpdf iconXINLUDA XL9535QF24
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.8217$ 0.82
10+$ 0.6538$ 6.54
30+$ 0.5683$ 17.05
100+$ 0.4859$ 48.59
500+$ 0.4601$ 230.05
1,000+$ 0.4343$ 434.30
Standard Packaging5000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/I/O Expanders
ManufacturerXINLUDA
PackagingQFN-24(4x4)
Interrupt OutputInterrupt Output
Operating Temperature-40℃~+85℃
Output TypePush-Pull
Number of I/O16
FeaturesReset function;Cascade and address expansion
Voltage - Supply2.3V~5.5V
Quiescent Supply Current250nA
Number of Supporting Devices8
Current - Output High(IOH)10mA
InterfaceI2C;SMBus
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging5000
Sales UnitPiece

Introduction

AI Translation

The device (XL9535/XL9555) is a 24-pin CMOS IC that provides 16-bit general-purpose parallel I/O (GPIO) expansion for most microcontroller families via an I²C/SMBus interface (SCL, SDA). The device is designed for VCC supply voltages from 2.3V to 5.5V. Improvements include higher drive capability, 5V I/O tolerance, lower supply current, independent I/O configuration, and a smaller package. The I/O expander provides a simple solution when additional I/O is needed for ACPI power switches, sensors, buttons, LEDs, fans, and similar peripherals. The device consists of two 8-bit configuration (input or output selection), input port, output port, and polarity inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The system master can enable each I/O as an input or output by writing to the I/O configuration bits. The data for each input or output is held in the corresponding input or output register. The polarity of the input port registers can be inverted via the polarity inversion register. All registers are readable by the system master. The device's open-drain interrupt (INT) output is asserted to notify the system master when any input state differs from its corresponding input port register state. The system master can use the power-on reset function to reset the device in the event of a timeout or other improper operation. Power-on reset sets all registers to their default values and initializes the I²C/SMBus state machine. Three hardware address pins (A0, A1, and A2) allow the fixed I²C bus address to be changed, enabling up to eight devices to share the same I²C/SMBus.

Features

AI Translation
  • I²C bus to 16-bit GPIO expander
  • Operating supply voltage range: 2.3V to 5.5V
  • Low standby current consumption
  • 5V-tolerant I/O ports
  • 400kHz fast-mode I²C bus clock frequency
  • Noise filter on SCL/SDA inputs
  • Internal power-on reset
  • Power-on glitch-free
  • Polarity inversion register
  • Up to 8 devices addressable via 3 hardware address pins
  • Open-drain active-low interrupt output
  • 16 I/O pins, default configured as 16 inputs
  • Latch-up testing exceeds 100mA per JESD 78 standard
  • ESD protection exceeds JESD 22: 2000V Human Body Model (HBM), 200V Machine Model (MM), and 1000V Charged Device Model (CDM)